FemtoClock
®
NG QUAD Universal
Frequency Translator
8T49N488
DATA SHEET
General Description
The 8T49N488 is a quad PLL with FemtoClock
®
NG technology, it
integrates low phase noise Frequency Translator / Synthesizer, Jitter
attenuation, and with alarm and monitoring functions suitable for
networking and communications applications. The device has four
fully independent PLLs, each PLL is able to generate any output
frequency in the 0.98MHz - 312.5MHz range and most output
frequencies in the 312.5MHz - 1,300MHz range (see Table 3 for
details). A wide range of input reference clocks and operation
reference clock may be used as the source for the output frequency.
Each PLL of 8T49N488 has three operating modes to support a very
broad spectrum of applications:
1) Frequency Synthesizer
Features
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Fourth generation FemtoClock
®
NG technology
Four fully independent PLLs
Universal Frequency Translator
TM
/Frequency Synthesizer and
Jitter attenuator
Outputs are programmable as LVPECL or LVDS
Programmable output frequency: 0.98MHz up to 1,300MHz
Two differential inputs support the following input levels:
LVPECL, LVDS, LVHSTL, HCSL
Input frequency range: 8kHz ~ 710MHz Low-Bandwidth
Input frequency range: 16MHz ~ 710MHz High-Bandwidth
REFCLK frequency range: 16MHz ~ 40MHz
Input clock monitor and alarm
Smoothed reference switch
Factory-set register configuration for power-up default state
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Synthesizes output frequencies from an external reference
clock REFCLK.
Fractional feedback division is used, so there are no
requirements for any specific input reference clock frequency to
produce the desired output frequency with a high degree of
accuracy.
2) High-Bandwidth Frequency Translator
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Applications: PCI Express, Computing, General Purpose
Translates any input clock in the 16MHz - 710MHz frequency
range into any supported output frequency.
This mode has a high PLL loop bandwidth in order to track input
reference changes, such as Spread-Spectrum Clock
modulation.
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Power-up default configuration
Configuration customized via One-Time Programmable ROM
Settings may be overwritten after power-up via I
2
C
I
2
C Serial interface for register programming
RMS phase jitter at 161.1328125MHz,using 40MHz REFCLK
(12kHz ~ 20MHz): 465fs (typical), Low Bandwidth Mode (FracN)
RMS phase jitter at 400MHz,using 40MHz REFCLK
(12kHz ~ 20MHz): 333fs (typical), Synthesizer Mode (Integer FB)
Full 2.5V ±5% supply mode
-40°C to 85°C ambient operating temperature
10mm X 10mm CABGA package
Lead-free (RoHS 6) packaging
3) Low-Bandwidth Frequency Translator
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Applications: Networking & Communications.
Translates any input clock in the 8kHz -710MHz frequency
range into any supported output frequency.
This mode supports PLL loop bandwidths in the 10Hz - 580Hz
range and makes use of an external REFCLK to provide
significant jitter attenuation.
Each PLL provides factory-programmed default power-up
configuration burned into One-Time Programmable (OTP) memory.
The configuration is specified by customer and are programmed by
IDT during the final test phase from an on-hand stock of blank
devices.
To implement other configurations, these power-up default settings
can be overwritten after power-up using the I
2
C interface and the
device can be completely reconfigured.
8T49N488 REVISION B 03/23/15
1
©2015 Integrated Device Technology, Inc.
8T49N488 DATA SHEET
Pin Descriptions and Pin Characteristics
Table 1. Pin Descriptions
Number
E5
C2, C3
D2,
D3
B7, C7
B6,
C6
G8, G7
F8,
F7
H3, G3
H4,
G4
B1,A2
B4, A6
A9, B9
D8, F9
J9, J8
H6, J4
J1, H1
F2, D1
A4, A5
D9, E9,
J6, J5
F1, E1
E4
C8
H7
G2
E2
C5
Name
REFCLK
CLK0A,
CLK1A
nCLK0A,
nCLK1A
CLK0B,
CLK1B
nCLK0B,
nCLK1B
CLK0C,
CLK1C
nCLK0C,
nCLK1C
CLK0D,
CLK1D
nCLK0D,
nCLK1D
Q0A, nQ0A
Q1A, nQ1A
Q0B, nQ0B
Q1B, nQ1B
Q0C, nQ0C
Q1C, nQ1C
Q0D, nQ0D
Q1D, nQ1D
LF0A, LF1A
LF0B, LF1B
LF0C, LF1C
LF0D, LF1D
Rsvd
Rsvd
Rsvd
Rsvd
LOCKA
LOCKB
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Input
Input
Input
Input
Output
Output
Type
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Description
Reference clock for device operation.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating (set by the
internal pullup and pulldown resistors).
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating (set by the
internal pullup and pulldown resistors).
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating (set by the
internal pullup and pulldown resistors).
Non-inverting differential clock input.
Inverting differential clock input. V
CC
2 default when left floating (set by the
internal pullup and pulldown resistors).
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
Loop filter connection node pins.LF0A is the output, LF1A is the input.
Loop filter connection node pins.LF0B is the output, LF1B is the input.
Loop filter connection node pins.LF0C is the output, LF1C is the input.
Loop filter connection node pins.LF0D is the output, LF1D is the input.
Reserved, connect to V
EE
Reserved, connect to V
EE
Reserved, connect to V
EE
Reserved, connect to V
EE
Lock Indicator - indicates that the PLL is in a locked condition.
LVCMOS/LVTTL interface levels.
Lock Indicator - indicates that the PLL is in a locked condition.
LVCMOS/LVTTL interface levels.
REVISION B 03/23/15
3
FEMTOCLOCK
®
NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
8T49N488 DATA SHEET
Table 1. Pin Descriptions
Number
E8
H5
Name
LOCKC
LOCKD
Output
Output
Type
Description
Lock Indicator - indicates that the PLL is in a locked condition.
LVCMOS/LVTTL interface levels.
Lock Indicator - indicates that the PLL is in a locked condition.
LVCMOS/LVTTL interface levels.
Pulldown
Input clock select. Selects the active differential clock input.
0 = CLK0A, nCLK0A (default)
1 = CLK1A, nCLK1A
Input clock select. Selects the active differential clock input.
0 = CLK0B, nCLK0B (default)
1 = CLK1B, nCLK1B
Input clock select. Selects the active differential clock input.
0 = CLK0C, nCLK0C (default)
1 = CLK1C, nCLK1C
Input clock select. Selects the active differential clock input.
0 = CLK0D, nCLK0D (default)
1 = CLK1D, nCLK1D
Bypasses the VCXO PLL.
0 = PLL Mode (default)
1 = PLL Bypassed
I
2
C Data Input/Output. Open drain.
I
2
C Clock Input. LVCMOS/LVTTL interface levels.
Analog power supply for PLLA
Output power supply for PLLA
Core power supply for PLLA
Analog power supply for PLLB
Output power supply for PLLB
Core power supply for PLLB
Analog power supply for PLLC
Output power supply for PLLC
Core power supply for PLLC
Analog power supply for PLLD
Output power supply for PLLD
Core power supply for PLLD
Negative supply for PLLA
Negative supply for PLLB
Negative supply for PLLC
Negative supply for PLLD
D4
CLK_SELA
Input
D6
CLK_SELB
Input
Pulldown
F6
CLK_SELC
Input
Pulldown
F4
CLK_SELD
Input
Pulldown
E6
G6
G5
C1
C4
B5
A7
D5
D7
E7
G9
F5
E3
J3
F3
A3, B2, B3
A8, B8, C9
H8, H9, J7
G1, H2, J2
PLL_BYPAS
S
SDATA
SCLK
V
CCA_A
V
CCO_A
V
CC_A
V
CCA_B
V
CCO_B
V
CC_B
V
CCA_C
V
CCO_C
V
CC_C
V
CCA_D
V
CCO_D
V
CC_D
V
EE_A
V
EE_B
V
EE_C
V
EE_D
Input
I/O
Input
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Pulldown
Pullup
Pullup
REVISION B 03/23/15
4
FEMTOCLOCK
®
NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
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