DATASHEET
ISL6729
Low-Cost, Single-Ended, Current-Mode PWM for Microcontroller Based Power
Converters
The
ISL6729
pulse width modulating (PWM) current mode
controller is designed for power conversion applications that
are based on a microcontroller, or other device, which can
generate a digital clock signal at the desired switching
frequency. Similar to the ISL684x family of products, the
ISL6729 provides the basic current mode PWM control
features, but eliminates the error amplifier, the oscillator, and
the reference. An external clock signal applied to the oscillator
input provides the time base and sets the maximum duty
cycle. The reduced feature set is ideal for those applications
where a microcontroller is available to provide the monitor and
control functions. The analog PWM provides the cycle-by-cycle
peak-current mode control, leaving the monitor and control
overhead to the microcontroller.
PART NUMBER
ISL6729
RISING UVLO
4.75V
MAX. DUTY CYCLE
100%
FN9152
Rev 3.00
December 21, 2016
Features
• 5V operation
• 1A MOSFET gate driver
• 400µA startup current
• 30ns propagation delay current sense to output
• Fast transient response with peak-current mode control
• Switching frequency to 2MHz
• 20ns rise and fall times with 1nF output load
• Maximum duty cycle determined by clock input duty cycle
• Tight tolerance current limit threshold
• Pb-free (RoHS compliant)
Applications
• Telecom and datacom power
• Wireless base station power
• File server power
• Industrial power systems
• PC power supplies
• Isolated buck and flyback regulators
• Boost regulators
Related Literature
• For a full list of related documents, visit our website
-
ISL6729
product page
Pin Configuration
ISL6729 (8 LD SOIC, MSOP)
TOP VIEW
COMP
N/C
CS
CLKS
1
2
3
4
8
7
6
5
N/C
VDD
OUT
GND
Ordering Information
PART
NUMBER
ISL6729IBZ
ISL6729IUZ (No longer available or supported)
NOTES:
1. Add -T suffix for 2.5k unit tape and reel option. Refer to
TB347
for details on reel specifications.
2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see product information page for
ISL6729.
For more information on MSL, see tech brief
TB363.
PART MARKING
6729IBZ
6729Z
TEMP. RANGE (°C)
-40 to +105
-40 to +105
PACKAGE
(RoHS COMPLIANT)
8 Ld SOIC
8 Ld MSOP
PKG.
DWG. #
M8.15
M8.118
FN9152 Rev 3.00
December 21, 2016
Page 1 of 8
ISL6729
Absolute Maximum Ratings
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to +6.5V
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(GND - 0.3V) to V
DD
+ 0.3V
Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to 6.5V
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A
ESD Classification
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . . . . . . . 2kV
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93). . . . . . . . . . 1kV
Thermal Information
Thermal Resistance (Typical,
Note 4)
JA
(°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
130
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see
TB493
Operating Conditions
Temperature Range
ISL6729Ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Supply Voltage Range (Typical)
ISL6729 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.75V to 5.25V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
4.
JA
is measured with the component mounted on a high-effective thermal conductivity test board in free air. See Tech Brief
TB379
for details.
5. All voltages are with respect to GND.
Electrical Specifications
PARAMETER
UNDERVOLTAGE LOCKOUT
START Threshold
STOP Threshold
Hysteresis
Start-Up Current, I
DD
Operating Current, I
DD
Operating Supply Current, I
D
CURRENT SENSE
Input Bias Current
CS Offset Voltage
Recommended operating conditions unless otherwise noted. Refer to
Figure 1 on page 2
and
Figure 2 on
page 3.
V
DD
= 5V, CLK = 50kHz, T
A
= -40 to +105°C (Note
6),
Typical values are at T
A
= +25°C
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4.15
4.00
-
V
DD
< START threshold
(Note
7)
Includes 1nF GATE loading
-
-
-
4.50
4.30
0.2
0.4
3.3
4.1
4.75
4.60
-
12
5.5
6.0
V
V
V
mA
mA
mA
V
CS
= 1V
V
CS
= 0V (Note
8)
V
CS
= 0V (Note
8)
-1.0
95
0.80
0.91
-
100
1.15
0.97
3.0
25
1.0
105
1.30
1.03
3.5
40
µA
mV
V
V
V/V
ns
COMP to PWM Comparator Offset Voltage
CS Input Signal, Maximum
Gain, A
CS
=
V
COMP
/V
CS
CS to OUT Delay
CLOCK
Input High Voltage Level, V
IH
Input Low Voltage Level, V
IL
Maximum Clock Rate
OUTPUT
Gate V
OH
Gate V
OL
Peak Output Current
Rise Time
Fall Time
0 < V
CS
< 910mV, V
FB
= 0V. (Note
8)
(Note
8)
2.5
-
-
-
(Note
8)
2
2.8
2.7
-
-
-
-
V
V
MHz
V
DD
- OUT, I
OUT
= -200mA
OUT - GND, I
OUT
= 200mA
C
OUT
= 1nF (Note
8)
C
OUT
= 1nF (Note
8)
C
OUT
= 1nF (Note
8)
-
-
1.0
-
-
1.0
1.0
-
20
20
2.0
2.0
-
40
40
V
V
A
ns
ns
FN9152 Rev 3.00
December 21, 2016
Page 4 of 8
ISL6729
Electrical Specifications
PARAMETER
PWM
Maximum Duty Cycle
Minimum Duty Cycle
NOTES:
Recommended operating conditions unless otherwise noted. Refer to
Figure 1 on page 2
and
Figure 2 on
page 3.
V
DD
= 5V, CLK = 50kHz, T
A
= -40 to +105°C (Note
6),
Typical values are at T
A
= +25°C (Continued)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
-
-
99
-
-
0
%
%
6. Specifications at -40°C are established by design, not production tested.
7. This is the V
DD
current consumed when the device is active but not switching. Does not include gate drive current.
8. Established by design, not 100% tested in production.
Pin Descriptions
CLK - This is the oscillator timing control pin. The operational
frequency and maximum duty cycle are set by applying a 5V
amplitude clock signal to CLK. The logic high duration defines
the maximum ON time for the output. A maximum clock rate
up to 2.0MHz is possible.
COMP - COMP is the input to the PWM comparator and is
typically controlled through an external error amplifier.
CS - This is the current sense input to the PWM comparator.
The range of the input signal is nominally 0 to 1.0V and has an
internal offset of 100mV.
GND - GND is the power and small signal reference ground for
all functions.
OUT - This is the drive output to the power switching device. It is
a high current output capable of driving the gate of a power
MOSFET with peak currents of 1.0A. This GATE output is
actively held low when V
DD
is below the UVLO threshold.
VDD - VDD is the 5V power connection for the IC. The IC will
operate from 4.75V to 5.25V. However, the accuracy of the
voltage clamp on the COMP signal, which determines the
overcurrent threshold, is dependent on the accuracy of VDD. A
tight tolerance on VDD will result in a tight overcurrent
threshold.
The total supply current will depend on the load applied to OUT.
Total I
DD
current is the sum of the operating current and the
average output current. Knowing the operating frequency, f,
and the MOSFET gate charge, Qg, the average output current
can be calculated from:
I
OUT
=
Qg
f
(EQ. 1)
Applications Information
Microcontrollers are becoming more popular for monitoring and
supervisory functions in power converters due to their flexibility,
capability, and declining prices. Many applications would like to
take advantage of this flexibility and use them to perform the
control loop function as well. There are many examples of
voltage mode control using digital signal processing techniques.
However, microcontrollers available today do not have the
execution speed required for peak current mode control at the
operational frequencies of modern switch-mode power supplies.
As such, they are unable to detect the peak current and
terminate the switching cycle within the few nanosecond
window required. The ISL6729 provides the analog circuitry
required to perform peak current control, but delegates the
oscillator function to the microcontroller. This arrangement
allows the microcontroller to control soft-start, maximum duty
cycle, and operational frequency of the power converter, as well
as performing the traditional overhead functions such as fault
monitoring and system interface.
Application of the ISL6729 is similar to the ISL684x family of
PWM converters except that the input bias voltage has been
changed to 5V and the oscillator, reference, and error amplifier
functions have been removed. An external digital clock signal,
such as the PWM output of a microcontroller, must be supplied
to control the frequency and maximum duty cycle. The
frequency of the applied clock signal and the frequency of
operation of the PWM are identical. The duty cycle of the clock
is the maximum duty cycle of the PWM. Soft-start may be
accomplished by incrementing the duty cycle of the applied
clock signal from zero to the maximum desired value in a time
frame appropriate for the application.
Figure 2 on page 3
illustrates how the ISL6729 may be used for
an interleaved power converter. In this example, three clock
signals of equal duty cycle, but phased 120° apart, are applied
to separate power stages. Each phase shares a common voltage
feedback signal, but uses separate current feedback signals
from each power stage for regulation. Excellent current sharing
behavior is assured since each phase must produce the same
peak current. Accuracy is determined by the variation of the
output inductor value and the feedback components.
Multiple output power supplies can be created in a similar
fashion. Only one clock signal is required if in-phase operation
is desired. Each stage may be independently controlled using
separate voltage and current feedback loops.
To optimize noise immunity, bypass VDD to GND with a
ceramic capacitor as close to the VDD and GND pins as
possible.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. A unique
section of the ground plane must be designated for high di/dt
currents associated with the output stage. VDD should be
bypassed directly to GND with good high frequency capacitors.
FN9152 Rev 3.00
December 21, 2016
Page 5 of 8
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