FM33256B
256-Kbit (32 K × 8) Integrated Processor
Companion with F-RAM
256-Kbit (32 K × 8) Serial (SPI) F-RAM
Features
■
Functional Overview
The FM33256B device integrates F-RAM memory with the most
commonly needed functions for processor-based systems.
Major features include nonvolatile memory, real time clock,
low-V
DD
reset, watchdog timer, nonvolatile event counter,
lockable 64-bit serial number area, and general purpose
comparator that can be used for a power-fail (NMI) interrupt or
any other purpose.
The FM33256B is a 256-Kbit nonvolatile memory employing an
advanced ferroelectric process. A ferroelectric random access
memory or F-RAM is nonvolatile and performs reads and writes
similar to a RAM. It provides reliable data retention for 151 years
while eliminating the complexities, overhead, and system-level
reliability problems caused by other nonvolatile memories. The
FM33256B is capable of supporting 10
14
read/write cycles, or
100 million times more write cycles than EEPROM.
The real time clock (RTC) provides time and date information in
BCD format. It can be permanently powered from an external
backup voltage source, either a battery or a capacitor. The
timekeeper uses a common external 32.768 kHz crystal and
provides a calibration mode that allows software adjustment of
timekeeping accuracy.
The processor companion includes commonly needed CPU
support functions. Supervisory functions include a reset output
signal controlled by either a low V
DD
condition or a watchdog
timeout. RST goes active when V
DD
drops below a
programmable threshold and remains active for 100 ms (max.)
after V
DD
rises above the trip point. A programmable watchdog
timer runs from 60 ms to 1.8 seconds. The timer may also be
programmed for a delayed start, which functions as a window
timer. The watchdog timer is optional, but if enabled it will assert
the reset signal for 100 ms if not restarted by the host within the
time window. A flag-bit indicates the source of the reset.
A comparator on PFI compares an external input pin to the
onboard 1.5 V reference. This is useful for generating a
power-fail interrupt (NMI) but can be used for any purpose. The
family also includes a programmable 64-bit serial number that
can be locked making it unalterable. Additionally it offers an
event counter that tracks the number of rising or falling edges
detected on a dedicated input pin. The counter can be
programmed to be nonvolatile under V
DD
power or
battery-backed using only V
BAK
. If V
BAK
is connected to a battery
or capacitor, then events will be counted even in the absence of
V
DD
.
For a complete list of related documentation, click
here.
256-Kbit ferroelectric random access memory (F-RAM)
❐
Logically organized as 32 K × 8
14
❐
High-endurance 100 trillion (10 ) read/writes
❐
151-year data retention (See the
Data Retention and
Endurance
table)
❐
NoDelay™ writes
❐
Advanced high-reliability ferroelectric process
High Integration Device Replaces Multiple Parts
❐
Serial nonvolatile memory
❐
Real time clock (RTC) with alarm
❐
Low V
DD
detection drives reset
❐
Watchdog window timer
❐
Early power-fail warning / NMI
❐
16-bit nonvolatile event counter
❐
Serial number with write-lock for security
Real-time Clock/Calendar
❐
Backup current at 2 V: 1.15
μA
at +25
°C
❐
Seconds through centuries in BCD format
❐
Tracks leap years through 2099
❐
Uses standard 32.768 kHz crystal (6 pF/12.5 pF)
❐
Software calibration
❐
Supports battery or capacitor backup
Processor Companion
❐
Active-low reset output for V
DD
and watchdog
❐
Programmable low-V
DD
reset thresholds
❐
Manual reset filtered and debounced
❐
Programmable watchdog window timer
❐
Nonvolatile event counter tracks system intrusions or other
events
❐
Comparator for power-fail interrupt or other use
❐
64-bit programmable serial number with lock
Fast serial peripheral interface (SPI)
❐
Up to 16-MHz frequency
❐
RTC, Supervisor controlled via SPI interface
❐
Supports SPI mode 0 (0, 0) and mode 3 (1, 1)
Low power consumption
❐
1.1 mA active current at 1 MHz
❐
150
μA
standby current
Operating voltage: V
DD
= 2.7 V to 3.6 V
Industrial temperature: –40
°C
to +85
°C
14-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Underwriters laboratory (UL) recognized
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Cypress Semiconductor Corporation
Document Number: 001-86213 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 5, 2015
FM33256B
Logic Block Diagram
Document Number: 001-86213 Rev. *C
Page 2 of 39
FM33256B
Contents
Pinout ................................................................................ 4
Pin Definitions .................................................................. 4
Overview ............................................................................ 5
Memory Architecture ................................................... 5
Processor Companion ..................................................... 5
Processor Supervisor .................................................. 5
Manual Reset .............................................................. 6
Reset Flags ................................................................. 6
Power Fail Comparator ............................................... 6
Event Counter ............................................................. 7
Serial Number ............................................................. 7
Alarm ........................................................................... 8
Real-time Clock Operation ............................................... 8
Backup Power ............................................................. 9
Trickle Charger .......................................................... 10
Calibration ................................................................. 10
Crystal Type .............................................................. 10
Layout Recommendations ............................................. 10
Register Map ................................................................... 13
Serial Peripheral Interface – SPI Bus ............................ 23
SPI Overview ............................................................. 23
SPI Modes ................................................................. 24
Power Up to First Access .......................................... 25
Command Structure .................................................. 25
WREN - Set Write Enable Latch ............................... 25
WRDI - Reset Write Enable Latch ............................. 25
Status Register and Write Protection ........................... 26
RDSR - Read Status Register ................................... 26
WRSR - Write Status Register .................................. 26
RDPC - Read Processor Companion ........................ 27
WRPC - Write Processor Companion ....................... 27
Memory Operation .......................................................... 28
Write Operation ......................................................... 28
Read Operation ......................................................... 28
Maximum Ratings ........................................................... 30
Operating Range ............................................................. 30
DC Electrical Characteristics ........................................ 30
Data Retention and Endurance ..................................... 32
Capacitance .................................................................... 32
Thermal Resistance ........................................................ 32
AC Test Conditions ........................................................ 32
Supervisor Timing .......................................................... 33
AC Switching Characteristics ....................................... 34
Ordering Information ...................................................... 35
Ordering Code Definitions ......................................... 35
Package Diagram ............................................................ 36
Acronyms ........................................................................ 37
Document Conventions ................................................. 37
Units of Measure ....................................................... 37
Document History Page ................................................. 38
Sales, Solutions, and Legal Information ...................... 39
Worldwide Sales and Design Support ....................... 39
Products .................................................................... 39
PSoC® Solutions ...................................................... 39
Cypress Developer Community ................................. 39
Technical Support ..................................................... 39
Document Number: 001-86213 Rev. *C
Page 3 of 39
FM33256B
Pinout
Figure 1. 14-pin SOIC pinout
CS
SO
CNT
V
BAK
X2
X1
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
ACS
SCK
SI
PFO
RST
PFI
Pin Definitions
Pin Name
CS
I/O Type
Input
Description
Chip Select.
This active LOW input activates the device. When HIGH, the device enters low-power
standby mode, ignores SCK and SI inputs, and the SO output is tristated. When LOW, the device
internally activates the SCK signal. A falling edge on CS must occur before every opcode.
Serial Clock.
SI and SO activity is synchronized to the serial clock. Inputs are latched on the rising
edge and outputs occur on the falling edge. Because the device is synchronous, the clock frequency
may be any value between 0 and 16 MHz and may be interrupted at any time.
Serial Input.
Data is input to the device on this pin. The pin is sampled on the rising edge of SCK and
is ignored at other times. It should always be driven to a valid logic level to meet I
DD
specifications.
Serial Output.
This is the data output pin. It is driven during a read and remains tristated at all other
times. Data transitions are driven on the falling edge of the serial clock.
Event Counter Input.
This input increments the counter when an edge is detected on this pin. The
polarity is programmable and the counter value is nonvolatile or battery-backed, depending on the
mode. This pin should be tied to ground if unused.
Alarm/Calibration/SquareWave.
This is an open-drain output that requires an external pull-up
resistor. In normal operation, this pin acts as the active-low alarm output. In Calibration mode,
a 512 Hz square-wave is driven out. In SquareWave mode, the user may select a frequency of 1, 512,
4096, or 32768 Hz to be used as a continuous output. The SquareWave mode is entered by clearing
the AL/SW and CAL bits in the register 18h.
SCK
Input
SI
[1]
SO
[1]
CNT
Input
Output
Input
ACS
Output
X1, X2
RST
PFI
PFO
V
BAK
Input/Output 32.768 kHz crystal connection. These pins should be left unconnected if RTC is not used.
Input/Output
Reset.
This active-low output is open drain with weak pull-up. It is also an input when used as a manual
reset. This pin should be left floating if unused.
Input
Output
Early Power-fail Input.
Typically connected to an unregulated power supply to detect an early power
failure. This pin must be tied to ground if unused.
Early Power-fail Output.
This pin is the early power-fail output and is typically used to drive a micro-
controller NMI pin. PFO drives LOW when the PFI voltage is < 1.5 V.
Power supply
Backup supply voltage.
Connected to a 3 V battery or a large value capacitor. If no backup supply
is used, this pin should be tied to V
SS
and the VBC bit should be cleared in the RTC register 18h. The
trickle charger is UL recognized and ensures no excessive current when using a lithium battery.
Power supply Ground for the device. Must be connected to the ground of the system.
Power supply Power supply input to the device.
V
SS
V
DD
Note
1. SI may be connected to SO for a single pin data interface
.
Document Number: 001-86213 Rev. *C
Page 4 of 39
FM33256B
Overview
The FM33256B device combines a serial nonvolatile RAM with
a real time clock (RTC) and a processor companion. The
companion is a highly integrated peripheral including a
processor supervisor, analog comparator, a nonvolatile counter,
and a serial number. The FM33256B integrates these
complementary but distinct functions under a common interface
in a single package. The product is organized as two logical
devices. The first is a memory and the second is the companion
which includes all the remaining functions. From the system
perspective they appear to be two separate devices with unique
opcodes on the serial bus.
The memory is organized as a standalone nonvolatile SPI
memory using standard opcodes. The real time clock and
supervisor functions are accessed under their own opcodes. The
clock and supervisor functions are controlled by 30 special
function registers. The RTC alarm and some control registers are
maintained by the power source on the V
BAK
pin, allowing them
to operate from battery or backup capacitor power when V
DD
drops below a set threshold. Each functional block is described
below.
faults, power-up, and software lockups. It is an open drain output
with a weak internal pull-up to V
DD
. This allows other reset
sources to be wire-OR'd to the RST pin. When V
DD
is above the
programmed trip point, RST output is pulled weakly to V
DD
. If
V
DD
drops below the reset trip point voltage level (V
TP
), the RST
pin will be driven LOW. It will remain LOW until V
DD
falls too low
for circuit operation which is the V
RST
level. When V
DD
rises
again above V
TP
, RST continues to drive LOW for at least 30 ms
(t
RPU
) to ensure a robust system reset at a reliable V
DD
level.
After t
RPU
has been met, the RST pin will return to the weak
HIGH state. While RST is asserted, serial bus activity is locked
out even if a transaction occurred as V
DD
dropped below V
TP
. A
memory operation started while V
DD
is above V
TP
will be
completed internally.
Table 1
below shows how bits VTP(1:0) control the trip point of
the low-V
DD
reset. They are located in register 18h, bits 1 and 0.
The reset pin will drive LOW when V
DD
is below the selected V
TP
voltage, and the SPI interface and F-RAM array will be locked
out.
Figure 2
illustrates the reset operation in response to a low
V
DD
.
Table 1. VTP setting
VTP Setting
VTP1
0
0
1
1
VTP0
0
1
0
1
2.6 V
2.75 V
2.9 V
3.0 V
Figure 2. Low V
DD
Reset
Memory Architecture
The FM33256B is available with 256-Kbit of memory. The device
uses two-byte addressing for the memory portion of the chip.
This makes the device software compatible with its standalone
memory counterparts, such as the FM25W256.
The memory array is logically organized as 32,768 × 8 bits and
is accessed using an industry-standard serial peripheral
interface (SPI) bus. The memory is based on F-RAM technology.
Therefore it can be treated as RAM and is read or written at the
speed of the SPI bus with no delays for write operations. It also
offers effectively unlimited write endurance unlike other
nonvolatile memory technologies. The SPI protocol is described
on
page 23.
The memory array can be write-protected by software. Two bits
(BP1, BP0) in the Status Register control the protection setting.
Based on the setting, the protected addresses cannot be written.
The Status Register & Write Protection is described in more
detail on
page 26.
V
DD
V
TP
t
RPU
RST
A watchdog timer can also be used to drive an active reset signal.
The watchdog is a free-running programmable timer. The
timeout period can be software programmed from 60 ms to 1.8
seconds in 60 ms increments via a 5-bit nonvolatile setting
(register 0Ch).
Figure 3. Watchdog Timer
Processor Companion
In addition to nonvolatile RAM, the FM33256B incorporates a
real time clock with alarm and highly integrated processor
companion. The companion includes a low-V
DD
reset, a
programmable watchdog timer, a 16-bit nonvolatile event
counter, a comparator for early power-fail detection or other
purposes, and a 64-bit serial number.
100 ms
clock
Timebase
WR(3:0) = 1010b to restart
Down Counter
Watchdog
Timer Settings
Processor Supervisor
Supervisors provide a host processor two basic functions:
Detection of power supply fault conditions and a watchdog timer
to escape a software lockup condition. The FM33256B has a
reset pin (RST) to drive a processor reset input during power
RST
WDE
Document Number: 001-86213 Rev. *C
Page 5 of 39
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