The PES12NT3 supports static lane reversal. For example, lane
reversal for upstream port A may be configured by asserting the PCI
Express Port A Lane Reverse (PEALREV) input signal or through serial
EEPROM or SMBus initialization. Lane reversal for ports B and C may
be enabled via a configuration space register, serial EEPROM, or the
SMBus.
Product Description
Utilizing standard PCI Express interconnect, the PES12NT3 provides
the most efficient high-performance I/O connectivity solution for applica-
tions requiring high throughput, low latency, and simple board layout
with a minimum number of board layers. With support for non-trans-
parent bridging, the PES12NT3, as a standalone switch or as a chipset
with IDT PCIe System Interconnect Switches, enables multi-host and
intelligent I/O applications requiring inter-domain communication. The
PES12NT3 provides 48 Gbps (6 GBps) of aggregated, full-duplex
switching capacity through 12 integrated serial lanes, using proven and
robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in
both directions and is fully compliant with PCI Express Base specifica-
tion 1.0a.
The PES12NT3 is based on a flexible and efficient layered architec-
ture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers in compliance with PCI Express Base specification
Revision 1.0a. The PES12NT3 can operate either as a store and
forward or cut-through switch depending on the packet size and is
designed to switch memory and I/O transactions. It supports eight Traffic
Classes (TCs) and one Virtual Channel (VC) with sophisticated resource
management. This includes round robin port arbitration, guaranteeing
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February 19, 2009
IDT 89HPES12NT3 Data Sheet
CPU
PES12NT3
CPU
PES12NT3
CPU
PES12NT3
PCIe System Interconnect Switch
PCIe System Interconnect Switch
Embedded
CPU
Embedded
CPU
SATA / SAS
Embedded
CPU
GbE / 10GigE
FC
Figure 2 PCIe System Interconnect Architecture Block Diagram
Controller 1
CPU
Controller 2
CPU
PES12N3
Cache Maint. &
Possible Data Flow
x4 PCIe
x4 PCIe
PES12N3
x4 PCIe
FC
Controller
FC
Controller
Storage
To Server
FC 2Gb/s and
4Gb/s
FC 2Gb/s and
4Gb/s
To Server
Figure 3 Dual Host Storage System
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February 19, 2009
IDT 89HPES12NT3 Data Sheet
Pin Description
The following tables list the functions of the pins provided on the PES12NT3. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
PEALREV
Type
I
Name/Description
PCI Express Port A Lane Reverse.
When this bit is asserted, the lanes of
PCI Express Port A are reversed. This value may be overridden by modify-
ing the value of the PALREV bit in the PA_SWCTL register.
PCI Express Port A Serial Data Receive.
Differential PCI Express receive
pairs for port A.
PCI Express Port A Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port A
PCI Express Port B Lane Reverse.
When this bit is asserted, the lanes of
PCI Express Port B are reversed. This value may be overridden by modify-
ing the value of the PBLREV bit in the PA_SWCTL register.
PCI Express Port B Serial Data Receive.
Differential PCI Express receive
pairs for port B.
PCI Express Port B Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port B
PCI Express Port C Lane Reverse.
When this bit is asserted, the lanes of
PCI Express Port C are reversed. This value may be overridden by modify-
ing the value of the PCLREV bit in the PA_SWCTL register.
PCI Express Port C Serial Data Receive.
Differential PCI Express receive
pairs for port C.
PCI Express Port C Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port C
PCI Express Reference Clock.
Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
PCI Express Reference Clock Mode Select.
These signals select the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 1 PCI Express Interface Pins
PEARP[3:0]
PEARN[3:0]
PEATP[3:0]
PEATN[3:0]
PEBLREV
I
O
I
PEBRP[3:0]
PEBRN[3:0]
PEBTP[3:0]
PEBTN[3:0]
PECLREV
I
O
I
PECRP[3:0]
PECRN[3:0]
PECTP[3:0]
PECTN[3:0]
PEREFCLKP[1:0]
PEREFCLKN[1:0]
I
O
I
REFCLKM
I
Signal
MSMBADDR[4:1]
MSMBCLK
Type
I
I/O
Name/Description
Master SMBus Address.
These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
Master SMBus Clock.
This bidirectional signal is used to synchronize
transfers on the master SMBus. It is active and generating the clock only
when the EEPROM is being accessed.
Master SMBus Data.
This bidirectional signal is used for data on the mas-
ter SMBus.
Table 2 SMBus Interface Pins (Part 1 of 2)
MSMBDAT
I/O
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February 19, 2009
IDT 89HPES12NT3 Data Sheet
Signal
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
Type
I
I/O
I/O
Name/Description
Slave SMBus Address.
These pins determine the SMBus address to
which the slave SMBus interface responds.
Slave SMBus Clock.
This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
Slave SMBus Data.
This bidirectional signal is used for data on the slave
SMBus.
Table 2 SMBus Interface Pins (Part 2 of 2)
Signal
GPIO[0]
Type
I/O
Name/Description
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PEBRSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port B
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PECRSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port C
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PALINKUPN
Alternate function pin type: Output
Alternate function: Port A link up status output
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PBLINKUPN
Alternate function pin type: Output
Alternate function: Port B link up status output
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PCLINKUPN
Alternate function pin type: Output
Alternate function: Port C link up status output
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: FAILOVERP
Alternate function pin type: Input
Alternate function: NTB upstream port failover
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
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