Freescale Semiconductor, Inc.
Data Sheet: Technical Data
Document Number: KL14P80M48SF0
Rev 5 08/2014
Kinetis KL14 Sub-Family
48 MHz Cortex-M0+ Based Microcontroller
Designed with efficiency in mind. Compatible with all other
Kinetis L families as well as Kinetis K1x family. General purpose
MCU featuring market leading ultra low-power to provide
developers an appropriate entry-level 32-bit solution.
This product offers:
• Run power consumption down to 47 μA/MHz in very low
power run mode
• Static power consumption down to 2 μA with full state
retention and 4 μs wakeup
• Ultra-efficient Cortex-M0+ processor running up to 48MHz
with industry leading throughput
• Memory option is up to 128 KB flash and 16 KB RAM
• Energy-saving architecture is optimized for low power with
90 nm TFS technology, clock and power gating techniques,
and zero wait state flash memory controller
MKL14ZxxVFM4
MKL14ZxxVFT4
MKL14ZxxVLH4
MKL14ZxxVLK4
32-pin QFN (FM)
48-pin QFN (FT)
5 x 5 x 1 Pitch 0.5 mm 7 x 7 x 1 Pitch 0.5 mm
64-pin LQFP (LH)
80-pin LQFP (LK)
10 x 10 x 1.4 Pitch 0.5 12 x 12 x 1.4 Pitch 0.5
mm
mm
Performance
• 48 MHz ARM
®
Cortex
®
-M0+ core
Memories and memory interfaces
• Up to 64 KB program flash memory
• Up to 8 KB SRAM
Human-machine interface
• Up to 70 general-purpose input/output (GPIO)
Communication interfaces
• Two 8-bit SPI modules
• One low power UART module
• Two UART modules
• Two I2C module
System peripherals
• Nine low-power modes to provide power optimization
Analog Modules
based on application requirements
• COP Software watchdog
• 12-bit SAR ADC
• 4-channel DMA controller, supporting up to 63 request
• Analog comparator (CMP) containing a 6-bit DAC
sources
and programmable reference input
• Low-leakage wakeup unit
• SWD debug interface and Micro Trace Buffer
Timers
• Bit Manipulation Engine
• Six channel Timer/PWM (TPM)
• Two 2-channel Timer/PWM modules
Clocks
• Periodic interrupt timers
• 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator
• 16-bit low-power timer (LPTMR)
• Multi-purpose clock source
• Real time clock
• 1 kHz LPO clock
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): -40 to 105°C
Security and integrity modules
• 80-bit unique identification number per chip
Freescale reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products. © 2012–2014 Freescale
Semiconductor, Inc. All rights reserved.
Ordering Information
Part Number
Flash (KB)
MKL14Z32VFM4
MKL14Z64VFM4
MKL14Z32VFT4
MKL14Z64VFT4
MKL14Z32VLH4
MKL14Z64VLH4
MKL14Z32VLK4
MKL14Z64VLK4
32
64
32
64
32
64
32
64
Memory
SRAM (KB)
4
8
4
8
4
8
4
8
28
28
40
40
54
54
70
70
Maximum number of I\O's
Related Resources
Type
Selector Guide
Product Brief
Reference
Manual
Data Sheet
Chip Errata
Package
drawing
Description
The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Resource
Solution Advisor
The Product Brief contains concise overview/summary information to KL1 Family Product Brief
1
enable quick evaluation of a device for design suitability.
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
The Data Sheet includes electrical characteristics and signal
connections.
The chip mask set Errata provides additional or corrective
information for a particular device mask set.
Package dimensions are provided in package drawings.
KL14P80M48SF0RM
1
KL14P80M48SF0
1
KINETIS_L_xN97F
2
QFN 32-pin: 98ASA00473D
1
QFN 48-pin: 98ASA00466D
1
LQFP 64-pin: 98ASS23234W
1
LQFP 80-pin: 98ASS23174W
1
1. To find the associated resource, go to
http://www.freescale.com
and perform a search using this term.
2. To find the associated resource, go to
http://www.freescale.com
and perform a search using this term with the “x”
replaced by the revision of the device you are using.
Figure 1
shows the functional modules in the chip.
2
Freescale Semiconductor, Inc.
Kinetis KL14 Sub-Family, Rev5 08/2014.
Kinetis KL14 Family
ARM Cortex-M0+
Core
Debug
interfaces
Interrupt
controller
MTB
System
Internal
watchdog
Memories and
Memory Interfaces
Program
flash
Clocks
Phase-
locked loop
Frequency-
locked loop
Low/high
frequency
oscillator
DMA
RAM
BME
Internal
reference
clocks
and Integrity
Internal
watchdog
Security
Analog
12-bit ADC
x1
Timers
Timers
1x6ch+2x2ch
Low
power timer
x1
Communication
Interfaces
I
C
x2
Low power
UART
x1
SPI
x2
UART
x2
2
Human-Machine
Interface (HMI)
GPIOs
with
interrupt
Analog
comparator
x1
6-bit DAC
Periodic
interrupt
timers
RTC
LEGEND
Migration difference from KL04 family
Figure 1. Functional block diagram
Kinetis KL14 Sub-Family, Rev5 08/2014.
3
Freescale Semiconductor, Inc.
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................6
2.2.1 Voltage and current operating requirements....... 7
2.2.2 LVD and POR operating requirements................7
2.2.3 Voltage and current operating behaviors.............8
2.2.4 Power mode transition operating behaviors........ 9
2.2.5 Power consumption operating behaviors............ 10
2.2.6 EMC radiated emissions operating behaviors..... 15
2.2.7 Designing with radiated emissions in mind..........16
2.2.8 Capacitance attributes.........................................16
2.3 Switching specifications...................................................16
2.3.1 Device clock specifications..................................16
2.3.2 General switching specifications......................... 17
2.4 Thermal specifications..................................................... 17
2.4.1 Thermal operating requirements......................... 17
2.4.2 Thermal attributes................................................18
3 Peripheral operating requirements and behaviors.................. 18
3.1 Core modules.................................................................. 18
3.1.1 SWD electricals .................................................. 18
3.2 System modules.............................................................. 20
3.3 Clock modules................................................................. 20
3.3.1 MCG specifications..............................................20
3.3.2 Oscillator electrical specifications........................22
3.4 Memories and memory interfaces................................... 24
3.4.1 Flash electrical specifications.............................. 24
3.5 Security and integrity modules........................................ 26
3.6 Analog............................................................................. 26
3.6.1 ADC electrical specifications............................... 26
3.6.2 CMP and 6-bit DAC electrical specifications....... 29
3.7 Timers..............................................................................31
3.8 Communication interfaces............................................... 31
3.8.1 SPI switching specifications................................ 31
3.8.2 Inter-Integrated Circuit Interface (I2C) timing...... 35
3.8.3 UART...................................................................37
Dimensions............................................................................. 37
4.1 Obtaining package dimensions....................................... 37
Pinout...................................................................................... 37
5.1 KL14 Signal Multiplexing and Pin Assignments...............37
5.2 KL14 pinouts....................................................................40
Ordering parts......................................................................... 44
6.1 Determining valid orderable parts....................................44
Part identification.....................................................................44
7.1 Description.......................................................................45
7.2 Format............................................................................. 45
7.3 Fields............................................................................... 45
7.4 Example...........................................................................45
Terminology and guidelines.................................................... 46
8.1 Definition: Operating requirement....................................46
8.2 Definition: Operating behavior......................................... 46
8.3 Definition: Attribute.......................................................... 46
8.4 Definition: Rating............................................................. 47
8.5 Result of exceeding a rating............................................ 47
8.6 Relationship between ratings and operating
requirements....................................................................48
8.7 Guidelines for ratings and operating requirements..........48
8.8 Definition: Typical value...................................................49
8.9 Typical value conditions.................................................. 50
9 Revision history.......................................................................50
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4
Freescale Semiconductor, Inc.
Kinetis KL14 Sub-Family, Rev5 08/2014.
Ratings
1 Ratings
1.1 Thermal handling ratings
Table 1. Thermal handling ratings
Symbol
T
STG
T
SDR
Description
Storage temperature
Solder temperature, lead-free
Min.
–55
—
Max.
150
260
Unit
°C
°C
Notes
1
2
1. Determined according to JEDEC Standard JESD22-A103,
High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020,
Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Table 2. Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
—
Max.
3
Unit
—
Notes
1
1. Determined according to IPC/JEDEC Standard J-STD-020,
Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Table 3. ESD handling ratings
Symbol
V
HBM
V
CDM
I
LAT
Description
Electrostatic discharge voltage, human body model
Electrostatic discharge voltage, charged-device
model
Latch-up current at ambient temperature of 105 °C
Min.
–2000
–500
–100
Max.
+2000
+500
+100
Unit
V
V
mA
Notes
1
2
3
1. Determined according to JEDEC Standard JESD22-A114,
Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101,
Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78,
IC Latch-Up Test.
Kinetis KL14 Sub-Family, Rev5 08/2014.
5
Freescale Semiconductor, Inc.
FPGA/CPLD
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