a
FEATURES
12-Bit Resolution
Low Gain TC: 2 ppm/ C typ
Fast TTL Compatible Data Latches
Single +5 V to +15 V Supply
Small 20-Lead 0.3" DIP and 20-Terminal Surface Mount
Packages
Latch Free (Schottky Protection Diode Not Required)
Low Cost
Ideal for Battery Operated Equipment
V
REF
19
CMOS 12-Bit
Buffered Multiplying DAC
AD7545
FUNCTIONAL BLOCK DIAGRAM
R
FB
20
AD7545
12-BIT
MULTIPLYING DAC
R
1
2
OUT 1
AGND
12
WR
17
CS
16
INPUT DATA LATCHES
3
12
DGND
18 V
DD
DB11–DB0
(PINS 4–15)
GENERAL DESCRIPTION
The AD7545 is a monolithic 12-bit CMOS multiplying DAC
with onboard data latches. It is loaded by a single 12-bit wide
word and directly interfaces to most 12- and 16-bit bus systems.
Data is loaded into the input latches under the control of the
CS
and
WR
inputs; tying these control inputs low makes the input
latches transparent, allowing direct unbuffered operation of the
DAC.
The AD7545 is particularly suitable for single supply operation
and applications with wide temperature variations.
The AD7545 can be used with any supply voltage from +5 V to
+15 V. With CMOS logic levels at the inputs the device dissi-
pates less than 0.5 mW for V
DD
= +5 V.
PIN CONFIGURATIONS
DIP
DGND
LCCC
DGND
AGND
OUT 1
PLCC
AGND
OUT 1
V
REF
AGND 2
DGND 3
DB11 (MSB) 4
DB10 5
DB9 6
19 V
REF
18 V
DD
17
WR
R
FB
OUT 1 1
20 R
FB
3
DB11 (MSB) 4
DB10 5
DB9 6
DB8 7
DB7 8
2
1 20 19
18 V
DD
3
DB11 (MSB) 4
DB10 5
DB9 6
DB8 7
DB7 8
9
DB6
2
1
20 19
PIN 1
IDENTIFIER
R
FB
V
REF
18 V
DD
17
WR
16
CS
15 DB0 (LSB)
14 DB1
AD7545
16
CS
AD7545
TOP VIEW
(Not to Scale)
17
WR
16
CS
15 DB0 (LSB)
14 DB1
AD7545
TOP VIEW
(Not to Scale)
TOP VIEW 15 DB0 (MSB)
(Not to Scale)
14 DB1
DB8 7
DB7 8
DB6 9
DB5 10
13 DB2
DB6
DB4
DB3
DB5
DB2
12 DB3
11 DB4
9 10 11 12 13
10 11 12 13
DB5
DB4
DB3
DB2
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
AD7545* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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DESIGN RESOURCES
•
AD7545 Material Declaration
•
PCN-PDN Information
•
Quality And Reliability
•
Symbols and Footprints
DOCUMENTATION
Application Notes
•
AN-225: 12-Bit Voltage-Output DACs for Single-Supply 5V
and 12V Systems
Data Sheet
•
AD7545: CMOS 12-Bit Buffered Multiplying DAC Data
Sheet
•
AD7545: Military Data Sheet
DISCUSSIONS
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SAMPLE AND BUY
Visit the product page to see pricing options.
REFERENCE MATERIALS
Solutions Bulletins & Brochures
•
Digital to Analog Converters ICs Solutions Bulletin
TECHNICAL SUPPORT
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number.
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AD7545–SPECIFICATIONS
(V
Parameter
STATIC PERFORMANCE
Resolution
Version
All
J, A, S
K, B, T
L, C, U
GL, GC, GU
J, A, S
K, B, T
L, C, U
GL, GC, GU
J, A, S
K, B, T
L, C, U
GL, GC, GU
All
All
J, K, L, GL
A, B, C, GC
S, T, U, GU
All
12
±
2
±
1
±
1/2
±
1/2
±
4
±
1
±
1
±
1
±
20
±
10
±
5
±
1
±
5
0.015
10
10
10
2
REF
= +10 V, V
OUT1
= O V, AGND = DGND unless otherwise noted)
V
DD
= +15 V
Limits
T
A
= + 25 C T
MIN,
T
MAX1
12
±
2
±
1
±
1/2
±
1/2
±
4
±
1
±
1
±
1
±
25
±
15
±
10
±
6
±
10
0.01
10
10
10
2
12
±
2
±
1
±
1/2
±
1/2
±
4
±
1
±
1
±
1
±
25
±
15
±
10
±
7
±
10
0.02
50
50
200
2
V
DD
= +5 V
Limits
T
A
= + 25 C T
MIN,
T
MAX1
12
±
2
±
1
±
1/2
±
1/2
±
4
±
1
±
1
±
1
±
20
±
10
±
6
±
2
±
5
0.03
50
50
200
2
Units
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
ppm/°C max
% per % max
nA max
nA max
nA max
µs
max
Test Conditions/Comments
Differential Nonlinearity
Gain Error (Using Internal RFB)
2
10-Bit Monotonic T
MIN
to T
MAX
12-Bit Monotonic T
MIN
to T
MAX
12-Bit Monotonic T
MIN
to T
MAX
12-Bit Monotonic T
MIN
to T
MAX
DAC Register Loaded with
1111 1111 1111
Gain Error Is Adjustable Using
the Circuits of Figures 4, 5, and 6
Typical Value is 2 ppm/°C for V
DD
= +5 V
∆V
DD
=
±
5%
DB0–DB11 = 0 V;
WR, CS
= 0 V
Gain Temperature Coefficient
3
∆Gain/∆Temperature
DC Supply Rejection
3
∆Gain/∆V
DD
Output Leakage Current at OUT1
DYNAMIC PERFORMANCE
Current Settling Time
3
To 1/2 LSB. OUT1 Load = 100
Ω.
DAC
Output Measured from Falling Edge of
WR, CS
= 0.
Propagation Delay
3
(from Digital
Input Change to 90%
of Final Analog Output)
Digital-to-Analog Glitch Inpulse
AC Feedthrough
5
At OUT1
REFERENCE INPUT
Input Resistance
(Pin 19 to GND)
ANALOG OUTPUT
Output Capacitance
3
C
OUT1
C
OUT1
DIGITAL INPUTS
Input High Voltage
V
IH
Input Low Voltage
V
IL
Input Current
6
I
IN
Input Capacitance
3
DB0–DB11
WR, CS
SWITCHING CHARACTERISTICS
7
Chip Select to Write Setup Time
t
CS
Chip Select to Write Hold Time
t
CH
Write Pulse Width
t
WR
Data Setup Time
t
DS
Data Hold Time
t
DH
POWER SUPPLY
I
DD
All
All
All
All
300
400
5
7
25
–
–
5
7
25
250
250
5
7
25
–
–
5
7
25
ns max
nV sec typ
mV p-p typ
kΩ min
kΩ max
OUT1 Load = 100
Ω,
C
EXT
= 13 pF
4
V
REF
= AGND
V
REF
=
±
10 V, 10 kHz Sinewave
Input Resistance TC = –300 ppm/°C typ
Typical Input Resistance = 11 kΩ
All
70
200
70
200
70
200
70
200
pF max
pF max
DB0–DB11 = 0 V,
WR, CS
= 0 V
DB0–DB11 = V
DD
,
WR, CS
= 0 V
All
All
All
All
All
All
2.4
0.8
±
1
5
20
280
200
0
250
175
140
100
10
2
100
10
2.4
0.8
±
10
5
20
380
270
0
400
280
210
150
10
2
500
10
13.5
1.5
±
1
5
20
180
120
0
160
100
90
60
10
2
100
10
13.5
1.5
±
10
5
20
200
150
0
240
170
120
80
10
2
500
10
V min
V max
µA
max
pF max
pF max
ns min
ns typ
ns min
ns min
ns typ
ns min
ns typ
ns min
mA max
µA
max
µA
typ
All Digital Inputs V
IL
or V
IH
All Digital Inputs 0 V to V
DD
All Digital Inputs 0 V to V
DD
t
CS
≥
t
WR
, t
CH
≥
0
V
IN
= 0 or V
DD
V
IN
= 0
V
IN
= 0
See Timing Diagram
All
All
All
All
All
NOTES
1
Temperature range as follows: J, K, L, GL versions, 0°C to +70°C; A, B, C, GC versions, –25°C to +85°C; S, T, U GU versions, –55°C to +125°C.
2
This includes the effect of 5 ppm max gain TC.
3
Guaranteed but not tested.
4
DB0–DB11 = 0 V to V
DD
or V
DD
to 0 V.
5
Feedthrough can be further reduced by connecting the metal lid on the ceramic package (Suffix D) to DGND.
6
Logic inputs are MOS gates. Typical input current (+25°C) is less than 1 nA.
7
Sample tested at +25°C to ensure compliance.
Specifications subject to change without notice.
–2–
REV. A
AD7545
t
CS
CHIP
SELECT
t
CH
V
DD
0
WRITE MODE:
MODE SELECTION
HOLD MODE:
EITHER
CS
OR
WR
HIGH, DATA BUS
(DB0–DB11) IS LOCKED OUT; DAC
HOLDS LAST DATA PRESENT WHEN
WR
OR
CS
ASSUMED HIGH STATE.
CS
AND
WR
LOW, DAC RESPONDS
TO DATA BUS (DB0–DB11) INPUTS.
t
WR
WRITE
V
DD
0
t
DS
DATA IN
(DB0–DB11)
V
IH
V
IL
DATA VALID
t
DH
V
DD
0
NOTES:
V
DD
= +5V; t
r
= t
f
= 20ns
V
DD
= +15V; t
r
= t
f
= 40ns
ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO
90% OF V
DD
.
TIMING MEASUREMENT REFERENCE LEVEL IS V
IH
+ V
IL
/2.
Write Cycle Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
(T
A
= + 25°C unless otherwise noted)
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, +17 V
Digital Input Voltage to DGND . . . . . . . –0.3 V, V
DD
+0.3 V
V
RFB
, V
REF
to DGND . . . . . . . . . . . . . . . . . . . . . . . . .
±
25 V
V
PIN1
to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW
Derates above +75°C . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature
Commercial (J, K, L, GL) Grades . . . . . . . . 0°C to +70°C
Industrial (A, B, C, GC) Grades . . . . . . . . –25°C to +85°C
Extended (S, T, U, GU) Grades . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7545 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
TERMINOLOGY
RELATIVE ACCURACY
ORDERING GUIDE
1
Maximum
Gain Error
T
A
= +25 C
V
DD
= +5 V
±
20 LSB
±
20 LSB
±
20 LSB
±
10 LSB
±
10 LSB
±
10 LSB
±
5 LSB
±
5 LSB
±
5 LSB
±
1 LSB
±
1 LSB
±
1 LSB
±
20 LSB
±
20 LSB
±
10 LSB
±
10 LSB
±
5 LSB
±
5 LSB
±
1 LSB
±
1 LSB
The amount by which the D/A converter transfer function
differs from the ideal transfer function after the zero and full-
scale points have been adjusted. This is an endpoint linearity
measurement.
DIFFERENTIAL NONLINEARITY
Model
2
AD7545JN
AD7545AQ
AD7545SQ
AD7545KN
AD7545BQ
AD7545TQ
AD7545LN
AD7545CQ
AD7545UQ
AD7545GLN
AD7545GCQ
AD7545GUQ
AD7545JP
AD7545SE
AD7545KP
AD7545TE
AD7545LP
AD7545UE
AD7545GLP
AD7545GUE
Temperature
Range
0°C to +70°C
–25°C to +85°C
–55°C to +125°C
0°C to +70°C
–25°C to +85°C
–55°C to +125°C
0°C to +70°C
–25°C to +85°C
–55°C to +125°C
0°C to +70°C
–25°C to +85°C
–55°C to +125°C
0°C to +70°C
–55°C to +125°C
0°C to +70°C
–55°C to +125°C
0°C to +70°C
–55°C to +125°C
0°C to +70°C
–55°C to +125°C
Relative
Accuracy
±
2 LSB
±
2 LSB
±
2 LSB
±
1 LSB
±
1 LSB
±
1 LSB
±
1/2 LSB
±
1/2 LSB
±
1/2 LSB
±
1/2 LSB
±
1/2 LSB
±
1/2 LSB
±
2 LSB
±
2 LSB
±
1 LSB
±
1 LSB
±
1/2 LSB
±
1/2 LSB
±
1/2 LSB
±
1/2 LSB
Package
Options
3
N-20
Q-20
Q-20
N-20
Q-20
Q-20
N-20
Q-20
Q-20
N-20
Q-20
Q-20
P-20A
E-20A
P-20A
E-20A
P-20A
E-20A
P-20A
E-20A
The difference between the measured change and the ideal
change between any two adjacent codes. If a device has a differ-
ential nonlinearity of less than 1 LSB it will be monotonic, i.e.,
the output will always increase for an increase in digital code
applied to the D/A converter.
PROPAGATION DELAY
This is a measure of the internal delay of the circuit and is mea-
sured from the time a digital input changes to the point at which
the analog output at OUT1 reaches 90% of its final value.
DIGITAL-TO-ANALOG GLITCH IMPULSE
This is a measure of the amount of charge injected from the
digital inputs to the analog outputs when the inputs change
state. It is usually specified as the area of the glitch in nV secs
and is measured with V
REF
= AGND and an ADLH0032CG as
the output op amp, C1 (phase compensation) = 33 pF.
NOTES
1
Analog Devices reserves the right to ship either ceramic (D-20) in lieu of cerdip
packages (Q-20).
2
To order MIL-STD-883, Class B process parts, add /883B to part number.
Contact local sales office for military data sheet. For U.S. Standard Military
DRAWING (SMD) see DESC drawing 5962-87702.
3
E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip.
REV. A
–3–
AD7545
CIRCUIT INFORMATION—D/A CONVERTER SECTION
Figure 1 shows a simplified circuit of the D/A converter section
of the AD7545 and Figure 2 gives an approximate equivalent
circuit. Note that the ladder termination resistor is connected to
AGND. R is typically 11 kΩ.
V
REF
R
R
R
R
power supply. To minimize power supply currents it is recom-
mended that the digital input voltages be as close as practicably
possible to the supply rails (V
DD
and DGND).
The AD7545 may be operated with any supply voltage in the
range 5
≤
V
DD
≤
15 volts. With V
DD
= +15 V the input logic
levels are CMOS compatible only, i.e., 1.5 V and 13.5 V.
BASIC APPLICATIONS
2R
2R
2R
2R
2R
2R
R
FB
OUT 1
AGND
DB11
(MSB)
DB10
DB9
DB1
DB0
(LSB)
Figure 1. Simplified D/A Circuit of AD7545
Figures 4 and 5 show simple unipolar and bipolar circuits using
the AD7545. Resistor R1 is used to trim for full scale. The
“G” versions (AD7545GLN, AD7545GCQ, AD7545GUD)
have a guaranteed maximum gain error of
±
1 LSB at +25°C
(V
DD
= +5 V), and in many applications it should be possible to
dispense with gain trim resistors altogether. Capacitor C1 provides
phase compensation and helps prevent overshoot and ringing when
using high speed op amps. Note that all the circuits of Figures 4, 5
and 6 have constant input impedance at the V
REF
terminal.
The circuit of Figure 1 can either be used as a fixed reference
D/A converter so that it provides an analog output voltage in the
range 0 to –V
IN
(note the inversion introduced by the op amp),
or V
IN
can be an ac signal in which case the circuit behaves as
an attenuator (2-Quadrant Multiplier). V
IN
can be any voltage
in the range –20
≤
V
IN
+ 20 volts (provided the op amp can
handle such voltages) since V
REF
is permitted to exceed V
DD
.
Table II shows the code relationship for the circuit of Figure 4.
V
DD
R2
*
20
R
FB
OUT1 1
AGND
DGND
3
ANALOG
COMMON
DB11–DB0
2
AD544L
(SEE TEXT)
C1
33pF
V
OUT
The binary weighted currents are switched between the OUT1
bus line and AGND by N-channel switches, thus maintaining a
constant current in each ladder leg independent of the switch
state.
The capacitance at the OUT1 bus line, C
OUT1
, is code depen-
dent and varies from 70 pF (all switches to AGND) to 200 pF
(all switches to OUT1).
One of the current switches is shown in Figure 2. The input
resistance at V
REF
(Figure 1) is always equal to R
LDR
(R
LDR
is
the R/2R ladder characteristic resistance and is equal to value
“R”). Since R
IN
at the V
REF
pin is constant, the reference termi-
nal can be driven by a reference voltage or a reference current,
ac or dc, of positive or negative polarity. (If a current source is
used, a low temperature coefficient external R
FB
is recommended
to define scale factor.)
TO LADDER
18
V
IN
R1
*
V
DD
19 V
REF
AD7545
FROM
INTERFACE
LOGIC
*
REFER TO TABLE I
Figure 4. Unipolar Binary Operation
Table I. Recommended Trim Resistor Values vs. Grades for
V
DD
= +5 V
AGND
OUT 1
Figure 2. N-Channel Current Steering Switch
CIRCUIT INFORMATION—DIGITAL SECTION
Trim
Resistor
R1
R2
J/A/S
500
Ω
150
Ω
K/B/T
200
Ω
68
Ω
L/C/U
100
Ω
33
Ω
GL/GC/GU
20
Ω
6.8
Ω
Figure 3 shows the digital structure for one bit.
The digital signals CONTROL and
CONTROL
are generated
from
CS
and
WR.
TO AGND SWITCH
V
IN
TO OUT1 SWITCH
Table II. Unipolar Binary Code Table for Circuit of Figure 4
Binary Number in DAC Register Analog Output
4095
–V
IN
4096
2048
–V
IN
4096
= –1/2 V
IN
1
–V
IN
4096
0 Volts
INPUT BUFFERS
1111
CONTROL
CONTROL
1111
1111
Figure 3. Digital Input Structure
1000
0000
0000
The input buffers are simple CMOS inverters designed so that
when the AD7545 is operated with V
DD
= 5 V, the buffers con-
vert TTL input levels (2.4 V and 0.8 V) into CMOS logic levels.
When V
IN
is in the region of 2.0 volts to 3.5 volts, the input
buffers operate in their linear region and draw current from the
–4–
0000
0000
0000
0000
0001
0000
REV. A
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