CY23FP12
200 MHz Field Programmable
Zero Delay Buffer
200 MHz Field Programmable Zero Delay Buffer
Features
■
Functional Description
The CY23FP12 is a high performance fully field-programmable
200 MHz zero delay buffer designed for high speed clock
distribution. The integrated PLL is designed for low jitter and
optimized for noise rejection. These parameters are critical for
reference clock distribution in systems using high performance
ASICs and microprocessors.
The CY23FP12 is fully programmable through volume or
prototype programmers, enabling the user to define an
application-specific Zero Delay Buffer with customized input and
output dividers, feedback topology (internal/external), output
inversions, and output drive strengths. For additional flexibility,
the user can mix and match multiple functions listed in
Table 2,
and assign a particular function set to any one of the four
possible S1-S2 control bit combinations. This feature enables
the implementation of four distinct personalities, selectable with
S1-S2 bits, on a single programmed silicon. The CY23FP12 also
features a proprietary auto power down circuit that shuts down
the device in case of a REF failure, resulting in less than 50
A
of current draw.
The CY23FP12 provides 12 outputs grouped in two banks with
separate power supply pins which can be connected
independently to either a 2.5 V or a 3.3 V rail.
Selectable reference input is a fault tolerance feature which
enables glitch-free switch over to a secondary clock source when
REFSEL is asserted/de-asserted.
For a complete list of related documentation, click
here.
Fully field-programmable
❐
Input and output dividers
❐
Inverting/non-inverting outputs
❐
Phase-locked loop (PLL) or fanout buffer configuration
10 MHz to 200 MHz operating range
Split 2.5 V or 3.3 V outputs
Two LVCMOS reference inputs
Twelve low skew outputs
❐
35 ps typical output-to-output skew (same frequency)
110 ps typical cycle-cycle jitter (same frequency)
Three-stateable outputs
Less than 50
A
shutdown current
Spread aware
28-pin SSOP
3.3 V operation
Industrial temperature available
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Logic Block Diagram
VDDC
VDDA
CLKA0
Lock Detect
CLKA1
CLKA2
CLKA3
REFSEL
REF1
REF2
FBK
M
N
100 to
400M Hz
PLL
1
2
3
4
X
CLKA4
CLKA5
VSSA
VDDB
CLKB0
CLKB1
CLKB2
CLKB3
Test Logic
S[2:1]
VSSC
Function
Selection
CLKB4
CLKB5
VSSB
Cypress Semiconductor Corporation
Document Number: 38-07246 Rev. *K
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 17, 2017
CY23FP12
Contents
Pin Configuration ............................................................. 3
Pin Description ................................................................. 4
Basic PLL Block Diagram ................................................ 5
Programmable Functions ................................................ 6
Field Programming the CY23FP12 ............................. 8
CyberClocks Software .............................................. 8
CY3672-USB Development Kit ................................... 8
CY23FP12 Frequency Calculation .................................. 8
Absolute Maximum Conditions ....................................... 9
Operating Conditions ....................................................... 9
DC Electrical Specifications .......................................... 10
Thermal Resistance ........................................................ 10
Switching Characteristics .............................................. 11
Switching Waveforms .................................................... 13
Test Circuits .................................................................... 14
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Drawing and Dimensions ............................... 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Document Number: 38-07246 Rev. *K
Page 2 of 19
CY23FP12
Pin Configuration
Figure 1. 28-pin SSOP pinout
Top View
REF2
REF1
CLKB0
CLKB1
V
SSB
CLKB2
CLKB3
V
DDB
V
SSB
CLKB4
CLKB5
V
DDB
V
DDC
S2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
REFSEL
FBK
CLKA0
CLKA1
V
SSA
CLKA2
CLKA3
V
DDA
V
SSA
CLKA4
CLKA5
V
DDA
V
SSC
S1
Document Number: 38-07246 Rev. *K
Page 3 of 19
CY23FP12
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Name
REF2
REF1
CLKB0
CLKB1
V
SSB
CLKB2
CLKB3
V
DDB
V
SSB
CLKB4
CLKB5
V
DDB
V
DDC
S2
S1
V
SSC
V
DDA
CLKA5
CLKA4
V
SSA
V
DDA
CLKA3
CLKA2
V
SSA
CLKA1
CLKA0
FBK
REFSEL
I/O
I
I
O
O
PWR
O
O
PWR
PWR
O
O
PWR
PWR
I
I
PWR
PWR
O
O
PWR
PWR
O
O
PWR
O
O
I
I
Type
Description
LVTTL/LVCMOS Input reference frequency, 5 V tolerant input.
LVTTL/LVCMOS Input reference frequency, 5 V tolerant input.
LVTTL
LVTTL
POWER
LVTTL
LVTTL
POWER
POWER
LVTTL
LVTTL
POWER
POWER
LVTTL
LVTTL
POWER
POWER
LVTTL
LVTTL
POWER
POWER
LVTTL
LVTTL
POWER
LVTTL
LVTTL
LVTTL
LVTTL
Clock output, Bank B.
Clock output, Bank B.
Ground for Bank B.
Clock output, Bank B.
Clock output, Bank B.
2.5 V or 3.3 V supply, Bank B.
Ground for Bank B.
Clock output, Bank B.
Clock output, Bank B.
2.5 V or 3.3 V supply, Bank B.
3.3 V core supply.
Select input.
Select input.
Ground for core.
2.5 V or 3.3 V supply, Bank A.
Clock output, Bank A.
Clock output, Bank A.
Ground for Bank A.
2.5 V or 3.3 V supply Bank A.
Clock output, Bank A.
Clock output, Bank A.
Ground for Bank A.
Clock output, Bank A.
CLock output, Bank A.
PLL feedback input.
Reference select input. When REFSEL = 0, REF1 is selected.
When REFSEL = 1, REF2 is selected.
Document Number: 38-07246 Rev. *K
Page 4 of 19
CY23FP12
Basic PLL Block Diagram
/1,/2,/3,/4,
/x,/2x
CLKB5
CLKB4
/1,/2,/3,/4,
/x,/2x
CLKB3
CLKB2
REF
/M
PLL
/1,/2,/3,/4,
/x,/2x
Output
Function
Select
Matrix
CLKB1
CLKB0
FBK
/N
/1,/2,/3,/4,
/x,/2x
CLKA5
CLKA4
/1,/2,/3,/4,
/x,/2x
CLKA3
CLKA2
/1,/2,/3,/4,
/x,/2x
CLKA1
CLKA0
Document Number: 38-07246 Rev. *K
Page 5 of 19
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