AS4C16M16MD1
256Mb MOBILE DDR SDRAM
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ................................................................................................... 3
2. FEATURES........................................................................................................................... 3
3. PIN DESCRIPTION............................................................................................................... 4
3.1 Signal Descriptions..........................................................................................................................5
4. BLOCK DIAGRAM ............................................................................................................... 7
4.1 Block Diagram .................................................................................................................................7
4.2 Simplified State Diagram ................................................................................................................. 8
5. FUNCTION DESCRIPTION .................................................................................................. 9
5.1 Initialization ...................................................................................................................................... 9
5.1.1 Initialization Flow Diagram .................................................................................................................. 10
5.2 Register Definition ......................................................................................................................... 12
5.2.1 Mode Register ............................................................................................................................ 12
5.3 Burst Definition .............................................................................................................................. 13
5.2.1.2 Burst Type ............................................................................................................................... 14
5.2.2 Extended Mode Register............................................................................................................ 14
5.2.2.1 Partial Array Self Refresh ....................................................................................................... 15
5.2.2.2 Temperature Compensated Self Refresh ............................................................................... 15
5.2.2.3 Output Drive Strength ............................................................................................................. 15
6. COMMANDS
.................................................................................................................... 16
7.OPERATION ........................................................................................................................ 21
7.1.
7.2.
7.4.
7.5.
Deselect........................................................................................................................................ 21
No Operation ................................................................................................................................ 21
Active ............................................................................................................................................ 22
Read ............................................................................................................................................. 23
7.5.1 Read to Read ......................................................................................................................................25
6.5.11 Burst Terminate................................................................................................................................. 30
7.6 Write .............................................................................................................................................. 30
7.6.1 Write to Write .....................................................................................................................................32
7.7 Precharge ...................................................................................................................................... 36
7.8 Auto Precharge ............................................................................................................................. 37
7.9 Refresh Requirements .................................................................................................................. 37
7.10 Auto Refresh ............................................................................................................................... 37
7.11 Self Referesh............................................................................................................................... 37
7.12 Power Down ................................................................................................................................ 39
7.13 Deep Power Down ...................................................................................................................... 41
7.14 Clock Stop ................................................................................................................................... 42
8. ELECTRICAL CHARACTERISTIC ......................................................................................43
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AS4C16M16MD1
256Mb MOBILE DDR SDRAM
8.1 Absolute Maximum Ratings ..........................................................................................................43
8.2 Input/Output Capacitance ............................................................................................................. 43
8.3 Electrical Characteristics and AC/DC Operating Conditions ........................................................ 44
8.3.1 Electrical Characteristics and AC/DC Operating Conditions............................................................... 44
8.4 IDD Specification Parameters and Test Conditions ..................................................................... 45
8.4.1 IDD Specification Parameters and Test Conditions ............................................................................ 45
8.5 AC Timings .................................................................................................................................... 47
8.5.2 Output Slew Rate Characteristics .......................................................................................................51
7.5.3 AC Overshoot/Undershoot Specification ............................................................................................. 51
8.5.4 AC Overshoot and Undershoot Definition ........................................................................................... 52
9. PACKAGE DIMENSION ..................................................................................................... 53
10. ORDERING INFORMATION............................................................................................. 54
11. REVISION HISTORY ........................................................................................................ 55
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AS4C16M16MD1
256Mb MOBILE DDR SDRAM
1. GENERAL DESCRIPTION
This AS4C16M16D1 is 268,435,456 bits synchronous double data rate Dynamic RAM. Each 67,108,864 bits bank is organized
as 8,192 rows by 512 columns by 16 bits, fabricated with Alliance Memory's high performance CMOS technology. This device uses a
double data rate architecture to achieve high- speed operation. The double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data words per clock cycle at the I/O balls. Range of operating
frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high
bandwidth and high performance memory system applications.
2. FEATURES
•AS4C16M16MD1
VDD/VDDQ = 1.7~1.95V
• Data width: x16
• Clock rate: 200MHz,166MHz , 133MHz
• Partial Array Self-Refresh(PASR)
• Auto Temperature Compensated Self-Refresh(ATCSR)
• Power Down Mode
• Deep Power Down Mode (DPD Mode)
• Programmable output buffer driver strength
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• Clock Stop capability during idle periods
• Auto Pre-charge option for each burst access
• Double data rate for data output
• Differential clock inputs (CK and CK )
• Bidirectional, data strobe (DQS)
• CAS Latency: 2 and 3
• Burst Length: 2, 4, 8 and 16
• Burst Type: Sequential or Interleave
• 64 ms Refresh period
• Interface: LVCMOS
• Operating Temperature Range
Extended (-25℃ to + 85
℃)
Industrial (-40℃ to + 85
℃)
Table 1. Ordering Information
Part Number
AS4C16M16MD1-6BCN
Clock
rate
166MHz
Package
60-ball FPBGA
(8.0X9.0 mm)
Temperature
Extended
Temp Range
-25°C to +85°C
B: indicates BGA package
C: indicates Extended temp
I: indicates Industrial temp (to follow at a later date)
N: Indicates lead free and ROHS compliant
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Mar, 28, 2013
AS4C16M16MD1
256Mb MOBILE DDR SDRAM
3. PIN DESCRIPTION
60- Ball FPBGA Assignment
TOP VIEW
1
2
3
4
5
6
7
8
9
A
VSS
DQ15
VSSQ
VDDQ
DQ0
VDD
B
VDDQ
DQ13
DQ
14
DQ
1
DQ2
VSSQ
C
VSSQ
DQ11
DQ
12
DQ
3
DQ4
VDDQ
D
VDDQ
DQ9
DQ
10
DQ
5
DQ6
VSSQ
E
VSSQ
UDQS
DQ8
DQ
7
LDQS
VDDQ
F
VSS
UDM
NC
NC
LDM
VDD
G
CKE
CK
/CK
/WE
/CAS
/RAS
H
A9
A11
A12
/CS
BA0
BA1
J
A6
A7
A8
A10/AP
A0
A1
K
VSS
A4
A5
A2
A3
VDD
Figure 1 — PIN DESCRIPTION
Mar, 28, 2013
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AS4C16M16MD1
256Mb MOBILE DDR SDRAM
3.1 Signal Descriptions
SIGNAL NAME
CK,/CK
TYPE
Input
DESCRIPTION
Clock: CK and CK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CK
and negative edge of CK. Input and output data is referenced to the
crossing of CK and CK (both directions of crossing). Internal clock
signals are derived from CK/CK.
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal
clock signals, and device input buffers and output drivers. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH
operation (all banks idle), or ACTIVE POWERDOWN (row ACTIVE in
any bank). CKE is synchronous for all functions except for SELF
REFRESH EXIT, which is achieved asynchronously. Input buffers,
excluding CK, CK and CKE, are disabled during power-down and self
refresh mode which are contrived for low standby power consumption.
Chip Select: CS enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS is
registered HIGH. CS provides for external bank selection on systems
with multiple banks. CS is considered part of the command code.
Command Inputs: RAS, CAS and WE (along with CS) define the
command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH along with that input data during a
WRITE access. DM is sampled on both edges of DQS. Although DM pins
are input-only, the DM loading matches the DQ and DQS loading. For
x16 devices, LDM corresponds to the data on DQ0-DQ7, UDM
corresponds to the data on DQ8-DQ15.
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE,
READ, WRITE or PRECHARGE command is being applied.
Address Inputs: provide the row address for ACTIVE commands, and
the column address and AUTO PRECHARGE bit for READ / WRITE
commands, to select one location out of the memory array in the
respective bank. The address inputs also provide the opcode during a
MODE REGISTER SET command.
Data Bus: Input / Output
Data Strobe: Output with read data, input with write data. Edge-aligned
with read data, centered with write data. Used to capture write data.
LDQS corresponds to the data on DQ0-DQ7, UDQS corresponds to the
data on DQ8-DQ15.
No Connect: No internal electrical connection is presen
CKE
Input
/CS
/RAS,/CAS,/WE
Input
Input
LDM,UDM
Input
BA0,BA1
Input
Input
A [n : 0]
DQ0-DQ15
I/O
I/O
-
Supply
Supply
Supply
Supply
LDQS,UDQS
NC
VDDQ
I/O Power Supply
I/O Ground
Power Supply
Ground
VSSQ
VDD
VSS
Table 1 — Signal Descriptions
Mar, 28, 2013
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