74LCX374
OCTAL D-TYPE FLIP FLOP NON-INVERTING (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
s
s
s
s
s
s
s
s
s
s
5V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED:
f
MAX
= 150 MHz (MIN.) at V
CC
= 3V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 374
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
DESCRIPTION
The 74LCX374 is a low voltage CMOS OCTAL
D-TYPE FLIP FLOP with 3 STATE OUTPUT
NON-INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for both inputs and outputs.
These 8 bit D-Type flip-flops are controlled by a
clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
Figure 1: Pin Connection And IEC Logic Symbols
te
le
so
b
O
ro
P
uc
d
s)
t(
outputs will be set to the logic state that were
setup at the D inputs.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
The Output control does not affect the internal
operation of flip flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
O
-
so
b
t
le
r
P
e
du
o
T&R
s)
t(
c
74LCX374MTR
74LCX374TTR
September 2004
Rev. 4
1/13
74LCX374
Table 4: Absolute Maximum Ratings
Symbol
V
CC
V
I
V
O
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage (OFF State)
DC Output Voltage (High or Low State) (note 1)
DC Input Diode Current
DC Output Diode Current (note 2)
DC Output Current
DC Supply Current per Supply Pin
DC Ground Current per Supply Pin
Storage Temperature
Lead Temperature (10 sec)
Parameter
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to +7.0
-0.5 to V
CC
+ 0.5
- 50
- 50
±
50
±
100
±
100
-65 to +150
300
Unit
V
V
V
V
mA
mA
mA
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) I
O
absolute maximum rating must be observed
2) V
O
< GND
Table 5: Recommended Operating Conditions
Symbol
V
CC
V
I
V
O
V
O
I
OH
, I
OL
I
OH
, I
OL
T
op
dt/dv
Supply Voltage (note 1)
Input Voltage
Output Voltage (OFF State)
Output Voltage (High or Low State)
Parameter
High or Low Level Output Current (V
CC
= 3.0 to 3.6V)
High or Low Level Output Current (V
CC
= 2.7V)
Operating Temperature
Input Rise and Fall Time (note 2)
1) Truth Table guaranteed: 1.5V to 3.6V
2) V
IN
from 0.8V to 2V at V
CC
= 3.0V
te
le
so
b
O
r
P
od
uc
)-
(s
t
b
O
so
t
le
r
P
e
Value
2.0 to 3.6
0 to 5.5
0 to 5.5
0 to V
CC
±
24
±
12
-55 to 125
0 to 10
du
o
s)
t(
c
mA
mA
°C
°C
Unit
V
V
V
V
mA
mA
°C
ns/V
3/13
74LCX374
Table 8: AC Electrical Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
50
50
50
50
500
500
500
500
2.5
2.5
2.5
2.5
50
500
2.5
50
500
2.5
C
L
(pF)
50
50
R
L
(Ω)
500
500
t
s
=
t
r
(ns)
2.5
2.5
-40 to 85 °C
Min.
1.5
1.5
1.5
1.5
1.5
1.5
2.5
2.5
1.5
1.5
3.3
3.3
150
Max.
9.5
8.5
9.5
8.5
8.5
7.5
Value
-55 to 125 °C
Min.
1.5
1.5
1.5
1.5
1.5
1.5
2.5
2.5
Max.
9.5
8.5
9.5
8.5
8.5
7.5
ns
ns
Unit
t
PLH
t
PHL
t
PZL
t
PZH
Propagation Delay
Time
Output Enable Time
to HIGH and LOW
level
Output Disable Time
from HIGH to LOW
level
Set-Up Time, HIGH
or LOW level
(Dn to CK)
Hold Time, HIGH or
LOW level
(Dn to CK)
CK Pulse Width,
HIGH
Clock Pulse
Frequency
Output To Output
Skew Time (note1,
2)
t
PLZ
t
PHZ
t
S
t
h
t
W
f
MAX
t
OSLH
t
OSHL
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= | t
PLHm
- t
PLHn
|, t
OSHL
= | t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
Table 4: Capacitive Characteristics
Symbol
Parameter
C
OUT
C
PD
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/8 (per
flip-flop)
et
l
so
b
O
C
IN
P
e
ro
uc
d
)-
(s
t
b
O
so
t
le
1.0
r
P
e
1.5
3.3
3.3
140
1.5
du
o
1.0
s)
t(
c
ns
ns
ns
ns
MHz
ns
Test Condition
Value
T
A
= 25 °C
Min.
Typ.
6
12
32
Max.
pF
pF
pF
Unit
V
CC
(V)
3.3
3.3
3.3
V
IN
= 0 to V
CC
V
IN
= 0 to V
CC
f
IN
= 10MHz
V
IN
= 0 or V
CC
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
(note 1)
5/13
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