Supertex inc.
Quad Power
Sequencing Controller
Features
►
Sequencing of four supplies, ICs, or subsystems
►
Independently programmable delays between open
drain PWRGD flags (5.0 to 200ms)
►
±10 to ±90V operation
►
Tracking in combination with Schottky diodes
►
Input supervisors including:
•
UV/OV lock out/enable
•
Power-on-Reset (POR)
►
Low power consumption, 0.4mA supply current
►
Available in a space saving 14-Lead SOIC package
PS10
General Description
Many
of today’s high performance FPGA’s, microprocessors,
DSP and industrial/embedded subsystems require sequencing
of the input power. Historically this has been accomplished
by: i) discretely using comparators, references & RC circuits;
ii) using expensive programmable controllers; or iii) with low
voltage sequencers requiring resistor drop downs and several
high voltage optocoupler or level shift components.
The PS10 saves board space, improves accuracy, eliminates
optocouplers or level shifts and reduces overall component
count by combining four timers, programmable input UV/OV
supervisors, a programmable POR, and four 90V open drain
outputs. A high reliability, high voltage, junction isolated process
allows the PS10 to be connected directly across the high voltage
input rails.
The power-on-reset interval (POR) may be programmed by a
capacitor on C
RAMP
. To sequence additional systems, multiple
PS10s may be daisy-chained together. If at any time the input
supply falls outside the UV/OV detector range, the PWRGD
outputs will immediately become IN-ACTIVE.
The PS10 is available in a space saving 14-Lead SOIC package.
Applications
►
►
►
►
►
►
►
►
►
Power supply sequencing
-48V telecom and networking distributed systems
-24V cellular and fixed wireless systems
-24V PBX systems
+48V storage systems
FPGA, microprocessor tracking
Industrial/embedded
system timing/sequencing
High voltage MEMs driver’s supply sequencing
High voltage display driver’s supply sequencing
Typical Application Circuit
GND or +48V
487k
6
14
/EN
+12V
COM
VIN
UV
PWRGD-D
PWRGD-C
PWRGD-B
PWRGD-A
RAMP
10
1
2
3
4
DC/DC
Converter
6.81k
5
7
9.76k
PS10
OV
VEE
TB
11
RTB
RTC
DC/DC
Converter
/EN
+5V
COM
TC
12
TD
13
RTD
DC/DC
Converter
/EN
+3.3V
COM
10nF
-48V or GND
DC/DC
Converter
/EN
+2.5V
COM
Notes:
1. Under Voltage Shutdown (UV) set to 37V.
2. Over Voltage Shutdown (OV) to 57.8V.
Doc.#DSFP-PS10
C080613
Supertex inc.
www.supertex.com
PS10
Ordering Information
Part Number
PS10NG-G
PS10NG-G-G M905
Package Option
14-Lead SOIC
14-Lead SOIC
Packing
53/Tube
2500/Reel
Pin Configuration
1
14
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter
V
EE
referenced to VIN pin
V
PWRGD
referenced to V
EE
voltage
V
UV
and V
OV
referenced to V
EE
voltage
Operating ambient temperature
Operating junction temperature
Storage temperature range
Power dissipation @ 25
C
O
Value
+0.3V to -100V
-0.3V to +100V
-0.3V to 12V
-40°C to +85°C
-40°C to +125°C
-65° to +150°C
750mW
Top Marking
PS10NG
14-Lead SOIC
(top view)
Product Marking
YWW
LLLLLLLL
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
Bottom Marking
CCCCCCCCC AAA
Y = Last Digit of Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
PWRGD Logic
Condition
Inactive (not ready)
Active (ready)
PWRGD-A/B/C/D
0
1
V
EE
Hi Z
Package may or may not include the following marks: Si or
14-Lead SOIC
Typical Thermal Resistance
Package
14-Lead SOIC
θ
ja
75
O
C/W*
Electrical Characteristics
(-10V ≤ V
Sym
V
EE
I
EE
V
UVH
V
UVL
V
UVHY
I
UV
V
OVH
V
OVL
V
OVHY
I
OV
Parameter
Supply voltage
Supply current
UV high threshold
UV low threshold
UV hysteresis
UV input current
OV high threshold
OV low threshold
OV hysteresis
OV input current
Supply
(Referenced to VIN pin)
IN
≤ -90V, T
A
= 25°C unless otherwise specified)
Min
-
-
#
#
#
-
#
#
#
-
-90
-
1.16
1.06
-
-
1.16
1.06
-
-
Typ
-
400
1.22
1.12
100
-
1.22
1.12
100
-
Max
-10
450
1.28
1.18
-
1.0
1.28
1.18
-
1.0
Units
V
µA
V
V
mV
nA
V
V
mV
nA
Conditions
---
V
EE
= -48V
Low to high transition
High to low transition
---
V
UV
= V
EE
+ 1.9V
Low to high transition
High to low transition
---
V
UV
= V
EE
+ 1.9V
OV and UV Control
(Referenced to VEE pin)
# Specifications apply over 0
O
C ≤ T
A
≤ 70
O
C
Doc.#DSFP-PS10
C080613
2
Supertex inc.
www.supertex.com
PS10
Electrical Characteristics
(cont.)
(-10V ≤ V
Sym
I
RAMP
t
PWRGD-A
t
PWRGD-B
t
PWRGD-B
t
PWRGD-C
t
PWRGD-C
t
PWRGD-D
t
PWRGD-D
Parameter
Ramp pin output current
Time from UV high to PWRGD-A
Maximum time from PWRGD-A to PWRGD-B
Minimum time from PWRGD-A to PWRGD-B
Maximum time from PWRGD-B to PWRGD-C
Minimum time from PWRGD-B to PWRGD-C
Maximum time from PWRGD-C to PWRGD-D
Minimum time from PWRGD-C to PWRGD-D
-
-
-
-
-
-
-
-
IN
≤ -90V, T
A
= 25°C unless otherwise specified)
Min
-
-
150
3.0
150
3.0
150
3.0
Typ
10
8.8
200*
5.0*
200*
5.0*
200*
5.0*
Max
-
-
250
8.0
250
8.0
250
8.0
Units
µA
ms
ms
ms
ms
ms
ms
ms
Conditions
---
V
EE
= -48V,
C
RAMP
= 10nF, see
typical application circuit
RTB = 120kΩ
RTD = 3.0kΩ
RTB = 120kΩ
RTD = 3.0kΩ
RTB = 120kΩ
RTD = 3.0kΩ
Power Good Timing
(Test Conditions: C
RAMP
= 10nF, V
UV
= V
EE
+ 1.9V, V
OV
= V
EE
+ 0.5V)
* Variations will track. For example if t
PWRGD-A
is 250ms, then so will be t
PWRGD-B/C/D
. Contact factory for tighter tolerance version.
Power Good Outputs
(Test Conditions: V
UV
= V
EE
+ 1.9V, V
OV
= V
EE
+ 0.5V)
V
PWRGD-X(hi)
V
PWRGD-X(lo)
I
PWRGD-X(lk)
Power good pin breakdown voltage
Power good pin output low voltage
Maximum leakage current
-
-
-
90
-
-
-
0.4
<1.0
-
0.5
10
V
V
µA
PWRGD-X = HI Z
I
PWRGD
= 1.0mA,
PWRGD-X = LOW
V
PWRGD
= 90V,
PWRGD-X = HI Z
Functional Block Diagram
Band Gap
Reference
VINT
UV
-
+
Regulator &
POR
VIN
VBG
Logic
-
+
UVLO
PWRGD-A
OV
PWRGD-B
PWRGD-C
PWRGD-D
VEE
VINT
10µA
+
Programmable
Timer
V
INT
1.2V
-
RAMP
TB
TC
TD
Doc.#DSFP-PS10
C080613
3
Supertex inc.
www.supertex.com
PS10
Functional Description
The PS10 is designed to sequence up to 4 power supply
modules, ICs or subsystems when the backplane voltage
is within the programmed under voltage and over voltage
limits. The power good open drain outputs are sequentially
enabled starting from PWRGD-A to PWRGD-D. The time
delay between power goods is programmable up to 200ms
simply by changing the value(s) of RTB, RTC, and RTD. The
initial time between satisfaction of the UV/OV supervisors &
PWRGD-A can be programmed with C
RAMP
.
The undervoltage and overvoltage shut down thresholds
can be programmed by means of the three resistor divider
formed by R1, R2 and R3. Since the input currents on the
UV and OV pins are negligible the resistor values may be
calculated as follows:
UV
OFF
= V
UVL
= 1.12 = (V
EEUV(off)
) x (R2+R3)/(R1+R2+R3)
OV
OFF
= V
OVL
= 1.22 = (V
EEOV(off)
) x R3/(R1+R2+R3)
Where (V
EEUV(off)
) and (V
EEOV(off)
) relative to V
EE
are under and
over voltage shut down threshold points.
If we select a divider current of 100µA at a nominal oper-
ating input voltage of 50V, then:
R1+R2+R3 = 50V/100µA = 500kΩ
From the second equation, for an OV shut down threshold of
65V, the value of R3 may be calculated.
OV
OFF
= 1.22 = (65xR3)/500kΩ
R3 = (1.22x 500kΩ)/65 = 9.38kΩ
The closest 1% value is 9.31kΩ.
From the first equation, for a UV shut down threshold of 35V,
the value of R2 can be calculated.
UV
OFF
= 1.12 = 35 x (R2+R3)/ 500kΩ
R2 = ((1.12 x 500kΩ)/35) – 9.76kΩ = 6.69kΩ
6.65kΩ is a standard 1% value
Then:
R1 = 500kΩ – R2 – R3 = 484.04kΩ.
487kΩ, is a standard 1% value.
From the calculated resistor values the OV and UV start up
threshold voltages can be calculated as follows:
UV
ON
= V
UVH
= 1.22 = (V
EEUV(on)
) x (R2+R3)/(R1+R2+R3)
OV
ON
= V
OVL
= 1.12 = (V
EEOV(on)
) x R3/(R1+R2+R3)
Where (V
EEUV(on)
) and (V
EEOV(on)
) are under and over voltage
start up threshold points relative to V
EE
.
Description of Operation
During the initial power application, the Power Good pins
are held low (rising with V
IN
). Once the internal under voltage
lock out has been satisfied, the circuit checks the input sup-
ply under voltage (UV) and over voltage (OV) sense circuits
to ensure that the input voltage is within programmed limits.
These limits are determined by the selected values for R1,
R2, and R3, which form a voltage divider.
At the same time, a 10µA current source is enabled, charging
the external capacitor connected to the ramp pin. The rise
time of the RAMP pin is determined by the value of the ca-
pacitor (10µA/C
RAMP
). When the ramp voltage reaches 8.8V,
the PWRGD-A pin will change into an active state. PWRGD-
B will change into an active state after a programmed time
delay from PWRGD-A inactive to active transition. PWRGD-
C will change into an active state after a programmed time
delay from PWRGD-B inactive to active transition. PWRGD-
D will change into an active state after a programmed time
delay from PWRGD-C inactive to active transition.
The controller continuously monitors the UV and OV pins as
long as the internal UVLO and POR circuits are satis-fied.
At any time during the start up cycle or thereafter, crossing
the UV low and OV high limits will cause an im-mediate dis-
charge on Cramp and reset on the power good pins. When
the input voltage returns to a value within the programmed
UV and OV limits, a new start up sequence will initiate im-
mediately.
Programming the Under and Over Voltage
Limits
The UV and OV pins are connected to comparators with
nominal 1.17V thresholds and 100mV of hysteresis (1.17V
±50mV). They are used to detect under voltage and over
voltage conditions at the input to the circuit. Whenever the
OV pin rises above its high threshold (1.22V) or the UV pin
falls below its low threshold (1.12V), the PWRGD outputs
immediately deactivate.
Calculations can be based on either the desired input volt-
age operating limits or the input voltage shutdown limits. In
the following equations the shutdown limits are assumed.
Doc.#DSFP-PS10
C080613
4
Supertex inc.
www.supertex.com
PS10
Then:
(V
EEUV(on)
) = 1.22 x (R1+R2+R3)/(R2+R3)
(V
EEUV(on)
) = 1.22 x (487k+6.65k+9.31k)/(6.65k+9.31k)
= 38.45V
And:
(V
EEOV(on)
) = 1.12 x (R1+R2+R3)/R3
(V
EEOV(on)
) = 1.12 x (487kΩ +6.65kΩ +9.31kΩ)/9.31kΩ
= 60.51V
Therefore, the circuit will start when the input supply voltage
is in the range of 38.45V to 60.51V.
PWRGD Flags Delay Programming
When the ramp voltage hits V
INT
- 1.17V, PWRGD-A be-
comes active indicating that the input supply voltage is within
the programmed limits. PWRGD-B goes active after a pro-
grammed time delay after PWRGD-A went active. PWRGD-
C goes active after a programmed time delay after PWRGD-
B went active. PWRGD-D goes active after a programmed
time delay after PWRGD-C went active.
The resistors connected from TB, TC, and TD to VEE pin
determines the delay times between the PWRGD flags.
The value of the resistors determines the capacitor charging
and discharging current of a triangular wave oscillator. The
oscillator output is fed into an 8-bit counter to generate the
desired time delay.
The respective time delay is defined by the following equa-
tion:
t
TX
= (255 x 2 x C
OSC
x V
PP
)/I
CD
and
I
CD
= V
BG
/ (4 x R
TX
)
Where:
t
TX
= Time delay between respective PWRGD flags
C
OSC
= 120pF (internal oscillator capacitor)
V
PP
= 8.2V (peak-to-peak voltage swing of oscillator)
I
CD
= Charge and discharge current of oscillator
V
BG
= 1.17V (internal band gap reference)
R
TX
= Programming resistor at TB, TC, or TD
Combining the two equations and solving for R
TX
yields:
R
TX
= (V
BG
x t
TX
) / (2040 x C
OSC
x V
PP
)
= 0.585 x 106 x t
TX
For a time delay of 200ms
R
TX
= 0.585 x 106 x 0.2 = 117kΩ
For a time delay of 5ms
R
TX
= 0.585 x 106 x 0.005 = 2.925kΩ
Undervoltage/Overvoltage Protection
GND
UV
OFF
UV
ON
V
IN
OV
ON
OV
OFF
PWRGD
SET
RESET
t
PWRGD-A
is the time delay from V
EEUV(on)
to PWRGD-A going
active. It can be approximated by:
t
PWRGD-A
= C
RAMP
x (V
INT
-1.17)/I
RAMP
where:
C
RAMP
= capacitor connected from RAMP pin to VEE pin
V
INT
= internal regulated power supply voltage (10V typ.)
I
RAMP
= 10µA charge current
Doc.#DSFP-PS10
C080613
5
Supertex inc.
www.supertex.com
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