DATASHEET
82C59A
CMOS Priority Interrupt Controller
The Intersil 82C59A is a high performance CMOS Priority
Interrupt Controller manufactured using an advanced 2m
CMOS process. The 82C59A is designed to relieve the
system CPU from the task of polling in a multilevel
priority system. The high speed and industry standard
configuration of the 82C59A make it compatible with
microprocessors such as 80C286, 80286, 80C86/88,
8086/88, 8080/85 and NSC800.
The 82C59A can handle up to eight vectored priority
interrupting sources and is cascadable to 64 without
additional circuitry. Individual interrupting sources can be
masked or prioritized to allow custom system configuration.
Two modes of operation make the 82C59A compatible with
both 8080/85 and 80C86/88/286 formats.
Static CMOS circuit design ensures low operating power.
The Intersil advanced CMOS process results in performance
equal to or greater than existing equivalent products at a
fraction of the power.
FN2784
Rev 6.00
Sep 8, 2015
Features
• Pb-Free Plus Anneal Available (RoHS Compliant)
• 12.5MHz, 8MHz and 5MHz Versions Available
• High Speed, “No Wait-State” Operation with 12.5MHz
80C286 and 8MHz 80C86/88
• Pin Compatible with NMOS 8259A
• 80C86/88/286 and 8080/85/86/88/286 Compatible
• Eight-Level Priority Controller, Expandable to
64 Levels
• Programmable Interrupt Modes
• Individual Request Mask Capability
• Fully Static Design
• Fully TTL Compatible
• Low Power Operation
- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . 10A Maximum
- ICCOP . . . . . . . . . . . . . . . . . . . . . . 1mA/MHz Maximum
• Single 5V Power Supply
• Commercial, Industrial and Military Operating
Temperature Ranges Available
FN2784 Rev 6.00
Sep 8, 2015
Page 1 of 23
82C59A
Ordering Information
PART NUMBER
5MHz
PART
MARKING
8MHz
CP82C59A
PART
MARKING
CP82C59A
12.5MHz
PART
MARKING
PACKAGE
28 Ld PDIP
TEMP
RANGE (°C)
0 to +70
PKG.
DWG. #
E28.6
CP82C59A-12
(No
CP82C59A-12
longer available,
recommended
replacement:
CP82C59A-12Z)
CP82C59A-12Z
(Note)
CP82C59AZ
(Note)
CS82C59A
(No longer
available,
recommended
replacement:
CS82C59AZ)
CP82C59AZ
CS82C59A
CP82C59A-12Z 28 Ld PDIP*
(Pb-Free)
28 Ld PLCC
0 to +70
0 to +70
E28.6
N28.45
CS82C59A-12
(No
CS82C59A-12
longer available,
recommended
replacement:
CS82C59A-12Z)
CS82C59A-1296
(No longer
available or
supported)
CS82C59A-12Z
(Note)
CS82C59A-12
CS82C59A96
(No
CS82C59A
longer available,
recommended
replacement:
CS82C59AZ96)
CS82C59AZ
(Note)
CS82C59AZ96
(Note)
IS82C59A
CS82C59AZ
CS82C59AZ
28 Ld PLCC
(Tape & Reel)
0 to +70
N28.45
CS82C59A-12Z 28 Ld PLCC
(Pb-Free)
0 to +70
0 to +70
N28.45
N28.45
CS82C59A-12Z96 CS82C59A-12Z 28 Ld PLCC
(Note)
(Pb-Free, Tape
& Reel)
IS82C59A-12
IS82C59A-12X96
IS82C59A-12
IS82C59A-12
28 Ld PLCC
28 Ld PLCC
(Tape & Reel)
IS82C59A
-40 to +85
-40 to +85
N28.45
N28.45
IS82C59AX96
No
IS82C59A
longer available,
recommended
replacement:
IS82C59A,
IS82C59AZX96)
IS82C59AZ
(Note)
IS82C59AZX96
(Note)
ID82C59A
MD82C59A/B
5962-8501601YA 5962-
5962-8501602YA
8501601YA
5962-85016023A
IS82C59AZ
IS82C59AZ
IS82C59A-12Z
(Note)
IS82C59A-12Z96
(Note)
IS82C59A-12Z
IS82C59A-12Z
28 Ld PLCC
(Pb-Free)
28 Ld PLCC
(Pb-Free, Tape
& Reel)
28 Ld CERDIP
-40 to +85
-40 to +85
N28.45
N28.45
ID82C59A
MD82C59A/B
5962-
8501602YA
5962-
85016023A
-40 to +85
-55 to +125
F28.6
F28.6
F28.6
J28.A
SMD#
28 Pad CLCC -
SMD#
-55 to +125
-55 to +125
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN2784 Rev 6.00
Sep 8, 2015
Page 2 of 23
82C59A
Pinouts
82C59A (PDIP, CERDIP)
TOP VIEW
CS 1
WR 2
RD 3
D7 4
D6 5
D5 6
D4 7
D3 8
D2 9
D1 10
D0 11
CAS 0 12
CAS 1 13
GND 14
28 V
CC
27 A0
26 INTA
25 IR7
24 IR6
23 IR5
22 IR4
21 IR3
20 IR2
19 IR1
18 IR0
17 INT
16 SP/EN
15 CAS 2
D6 5
D5 6
D4 7
D3 8
D2 9
D1 10
D0 11
12
CAS 0
13
CAS 1
14
GND
15
CAS 2
16
SP/ EN
17
INT
18
IR0
IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7
82C59A (PLCC, CLCC)
TOP VIEW
INTA
26
25 IR7
24 IR6
23 IR5
22 IR4
21 IR3
20 IR2
19 IR1
V
CC
28
WR
RD
CS
D7
A0
27
4
3
2
1
PIN
D7 - D0
RD
WR
A0
CS
CAS 2 - CAS 0
SP/EN
INT
INTA
IR0 - IR7
DESCRIPTION
Data Bus (Bidirectional)
Read Input
Write Input
Command Select Address
Chip Select
Cascade Lines
Slave Program Input Enable
Interrupt Output
Interrupt Acknowledge Input
Interrupt Request Inputs
Functional Diagram
INTA
DATA
BUS
BUFFER
INT
D
7
-D
0
CONTROL LOGIC
RD
WR
A
0
CS
READ/
WRITE
LOGIC
IN -
SERVICE
REG
(ISR)
PRIORITY
RESOLVER
INTERRUPT
REQUEST
REG
(IRR)
CAS 0
CAS 1
CAS 2
SP/EN
CASCADE
BUFFER
COMPARATOR
INTERNAL BUS
INTERRUPT MASK REG
(IMR)
FIGURE 1.
FN2784 Rev 6.00
Sep 8, 2015
Page 3 of 23
82C59A
Pin Description
SYMBOL
V
CC
GND
CS
WR
RD
D7 - D0
CAS0 - CAS2
SP/EN
TYPE
I
I
I
I
I
I/O
I/O
I/O
DESCRIPTION
V
CC
: The +5V power supply pin. A 0.1F capacitor between pins 28 and 14 is recommended for decoupling.
GROUND
CHIP SELECT: A low on this pin enables RD and WR communications between the CPU and the 82C59A. INTA
functions are independent of CS.
WRITE: A low on this pin when CS is low enables the 82C59A to accept command words from the CPU.
READ: A low on this pin when CS is low enables the 82C59A to release status onto the data bus for the CPU.
BIDIRECTIONAL DATA BUS: Control, status, and interrupt-vector information is transferred via this bus.
CASCADE LINES: The CAS lines form a private 82C59A bus to control a multiple 82C59A structure. These
pins are outputs for a master 82C59A and inputs for a slave 82C59A.
SLAVE PROGRAM/ENABLE BUFFER: This is a dual function pin. When in the Buffered Mode it can be used
as an output to control buffer transceivers (EN). When not in the Buffered Mode it is used as an input to
designate a master (SP = 1) or slave (SP = 0).
INTERRUPT: This pin goes high whenever a valid interrupt request is asserted. It is used to interrupt the CPU,
thus, it is connected to the CPU's interrupt pin.
INTERRUPT REQUESTS: Asynchronous inputs. An interrupt request is executed by raising an IR input (low to
high), and holding it high until it is acknowledged (Edge Triggered Mode), or just by a high level on an IR input
(Level Triggered Mode). Internal pull-up resistors are implemented on IR0 - 7.
INTERRUPT ACKNOWLEDGE: This pin is used to enable 82C59A interrupt-vector data onto the data bus by
a sequence of interrupt acknowledge pulses issued by the CPU.
ADDRESS LINE: This pin acts in conjunction with the CS, WR, and RD pins. It is used by the 82C59A to
decipher various Command Words the CPU writes and status the CPU wishes to read. It is typically connected
to the CPU A0 address line (A1 for 80C86/88/286).
INT
IR0 - IR7
O
I
INTA
A0
I
I
Functional Description
Interrupts in Microcomputer Systems
Microcomputer system design requires that I/O devices such
as keyboards, displays, sensors and other components
receive servicing in an efficient manner so that large
amounts of the total system tasks can be assumed by the
microcomputer with little or no effect on throughput.
The most common method of servicing such devices is the
Polled approach. This is where the processor must test each
device in sequence and in effect “ask” each one if it needs
servicing. It is easy to see that a large portion of the main
program is looping through this continuous polling cycle and
that such a method would have a serious, detrimental effect
on system throughput, thus, limiting the tasks that could be
assumed by the microcomputer and reducing the cost
effectiveness of using such devices.
CPU
CPU - DRIVEN
MULTIPLEXER
RAM
I/O (1)
ROM
I/O (2)
I/O (N)
FIGURE 2. POLLED METHOD
FN2784 Rev 6.00
Sep 8, 2015
Page 4 of 23
82C59A
A more desirable method would be one that would allow the
microprocessor to be executing its main program and only
stop to service peripheral devices when it is told to do so by
the device itself. In effect, the method would provide an
external asynchronous input that would inform the processor
that it should complete whatever instruction that is currently
being executed and fetch a new routine that will service the
requesting device. Once this servicing is complete, however,
the processor would resume exactly where it left off.
This is the Interrupt-driven method. It is easy to see that
system throughput would drastically increase, and thus,
more tasks could be assumed by the microcomputer to
further enhance its cost effectiveness.
The Programmable Interrupt Controller (PlC) functions as an
overall manager in an Interrupt-Driven system. It accepts
requests from the peripheral equipment, determines which of
the incoming requests is of the highest importance (priority),
ascertains whether the incoming request has a higher
priority value than the level currently being serviced, and
issues an interrupt to the CPU based on this determination.
Each peripheral device or structure usually has a special
program or “routine” that is associated with its specific
functional or operational requirements; this is referred to as a
“service routine”. The PlC, after issuing an interrupt to the
CPU, must somehow input information into the CPU that can
“point” the Program Counter to the service routine
associated with the requesting device. This “pointer” is an
address in a vectoring table and will often be referred to, in
this document, as vectoring data.
INT
CPU
82C59A Functional Description
PIC
RAM
I/O (1)
ROM
I/O (2)
The 82C59A is a device specifically designed for use in real
time, interrupt driven microcomputer systems. It manages
eight levels of requests and has built-in features for
expandability to other 82C59As (up to 64 levels). It is
programmed by system software as an I/O peripheral. A
selection of priority modes is available to the programmer so
that the manner in which the requests are processed by the
82C59A can be configured to match system requirements.
The priority modes can be changed or reconfigured
dynamically at any time during main program operation. This
means that the complete interrupt structure can be defined
as required, based on the total system environment.
I/O (N)
FIGURE 3. INTERRUPT METHOD
INTA
DATA
BUS
BUFFER
INT
D
7
- D
0
CONTROL LOGIC
RD
WR
A
0
CS
READ/
WRITE
LOGIC
IN
SERVICE
REG
(ISR)
PRIORITY
RESOLVER
INTERRUPT
REQUEST
REG
(IRR)
IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7
CAS 0
CAS 1
CAS 2
SP/EN
CASCADE
BUFFER
COMPARATOR
INTERNAL BUS
INTERRUPT MASK REG
(IMR)
FIGURE 4. 82C59A FUNCTIONAL DIAGRAM
FN2784 Rev 6.00
Sep 8, 2015
Page 5 of 23
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