19-5961; Rev 1; 9/11
10-Bit, 300ksps ADCs
with FIFO and Internal Reference
General Description
The MAX11618–MAX11621/MAX11624/MAX11625 are
serial 10-bit analog-to-digital converters (ADCs) with an
internal reference. These devices feature on-chip FIFO,
scan mode, internal clock mode, internal averaging,
and AutoShutdown™. The maximum sampling rate is
300ksps using an external clock. The MAX11624/
MAX11625 have 16 input channels, the MAX11620/
MAX11621 have 8 input channels, and the MAX11618/
MAX11619 have 4 input channels. These six devices
operate from either a +3V supply or a +5V supply, and
contain a 10MHz SPI™-/QSPI™-/MICROWIRE™-com-
patible serial port.
The MAX11618–MAX11621 are available in 16-pin
QSOP packages. The MAX11624/MAX11625 are avail-
able in 24-pin QSOP packages. All six devices are
specified over the extended -40°C to +85°C tempera-
ture range.
Features
o
Analog Multiplexer with Track/Hold
16 Channels (MAX11624/MAX11625)
8 Channels (MAX11620/MAX11621)
4 Channels (MAX11618/MAX11619)
o
Single Supply
2.7V to 3.6V (MAX11619/MAX11621/MAX11625)
4.75V to 5.25V
(MAX11618/MAX11620/MAX11624)
o
Internal Reference
2.5V (MAX11619/MAX11621/MAX11625)
4.096V (MAX11618/MAX11620/MAX11624)
o
External Reference: 1V to V
DD
o
16-Entry First-In/First-Out (FIFO)
o
Scan Mode, Internal Averaging, and Internal Clock
o
Accuracy: ±1 LSB INL, ±1 LSB DNL, No Missing
Codes Over Temperature
o
10MHz 3-Wire SPI-/QSPI-/MICROWIRE-Compatible
Interface
o
Small Packages
16-Pin QSOP (MAX11618–MAX11621)
24-Pin QSOP (MAX11624/MAX11625)
MAX11618–MAX11621/MAX11624/MAX11625
Applications
System Supervision
Data-Acquisition Systems
Industrial Control Systems
Patient Monitoring
Data Logging
Instrumentation
Ordering Information
PART
MAX11618EEE+T
MAX11619EEE+T
MAX11620EEE+T
MAX11621EEE+T
MAX11624EEG+T
MAX11625EEG+T
NUMBER
OF
INPUTS
4
4
8
8
16
16
SUPPLY
VOLTAGE
RANGE (V)
4.75 to 5.25
2.7 to 3.6
4.75 to 5.25
2.7 to 3.6
4.75 to 5.25
2.7 to 3.6
PIN-
PACKAGE
16 QSOP
16 QSOP
16 QSOP
16 QSOP
24 QSOP
24 QSOP
Note:
All devices are specified over the -40°C to +85°C operating
temperature range.
+Denotes
a lead(Pb)-free/RoHS-compliant package.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
10-Bit, 300ksps ADCs
with FIFO and Internal Reference
MAX11618–MAX11621/MAX11624/MAX11625
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND ..............................................................-0.3V to +6V
CS,
SCLK, DIN,
EOC,
DOUT to GND.........-0.3V to (V
DD
+ 0.3V)
AIN0–AIN14,
CNVST/AIN_,
REF to GND ...........................................-0.3V to (V
DD
+ 0.3V)
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (T
A
= +70°C)
16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW
24-Pin QSOP (derate 9.5mW/°C above +70°C)...........762mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
16 QSOP
Junction-to-Ambient Thermal Resistance (θ
JA
)...............105°C/W
Junction-to-Case Thermal Resistance (θ
JC
)......................37°C/W
24 QSOP
Junction-to-Ambient Thermal Resistance (θ
JA
)................88°C/W
Junction-to-Case Thermal Resistance (θ
JC
).......................34°C/W
Note 1:
Package thermal resistances were obtained usiˇng the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to
www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(V
DD
= 2.7V to 3.6V (MAX11619/MAX11621/MAX11625); V
DD
= 4.75V to 5.25V (MAX11618/MAX11620/MAX11624),
f
SAMPLE
= 300kHz, f
SCLK
= 4.8MHz (external clock, 50% duty cycle), V
REF
= 2.5V (MAX11619//MAX11621/MAX11625); V
REF
= 4.096V
(MAX11618/MAX11620/MAX11624), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
DC ACCURACY (Note 3)
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Offset Error Temperature
Coefficient
Gain Temperature Coefficient
Channel-to-Channel Offset
Matching
DYNAMIC SPECIFICATIONS (30kHz sine-wave input, 300ksps, f
SCLK
= 4.8MHz)
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
Full-Linear Bandwidth
SINAD
THD
SFDR
IMD
f
IN1
= 29.9kHz, f
IN2
= 30.1kHz
-3dB point
S/(N + D) > 61dB
Up to the 5th harmonic
62
-79
-81
-74
1
100
dB
dBc
dBc
dBc
MHz
kHz
(Note 4)
RES
INL
DNL
No missing codes over temperature
±0.5
±0.5
±2
±0.8
±0.1
10
±1.0
±1.0
±2.0
±2.0
Bits
LSB
LSB
LSB
LSB
ppm/°C
FSR
ppm/°C
LSB
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
10-Bit, 300ksps ADCs
with FIFO and Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 3.6V (MAX11619/MAX11621/MAX11625); V
DD
= 4.75V to 5.25V (MAX11618/MAX11620/MAX11624),
f
SAMPLE
= 300kHz, f
SCLK
= 4.8MHz (external clock, 50% duty cycle), V
REF
= 2.5V (MAX11619//MAX11621/MAX11625); V
REF
= 4.096V
(MAX11618/MAX11620/MAX11624), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
CONVERSION RATE
Power-Up Time
Acquisition Time
Conversion Time
External Clock Frequency
Aperture Delay
Aperture Jitter
ANALOG INPUT
Input Voltage Range
Input Leakage Current
Input Capacitance
INTERNAL REFERENCE
REF Output Voltage
REF Temperature Coefficient
Output Resistance
REF Output Noise
REF Power-Supply Rejection
EXTERNAL REFERENCE
REF Input Voltage Range
PSRR
V
REF
V
REF
= 2.5V (MAX11619/MAX11621/
MAX11625); V
REF
= 4.096V
(MAX11618/MAX11620/MAX11624),
f
SAMPLE
= 300ksps
V
REF
= 2.5V (MAX11619/MAX11621/
MAX11625); V
REF
= 4.096V
(MAX11618/MAX11620/MAX11624),
f
SAMPLE
= 0
1.0
TC
REF
MAX11618/MAX11620/MAX11624
MAX11619/MAX11621/MAX11625
MAX11618/MAX11620/MAX11624
MAX11619/MAX11621/MAX11625
4.024
2.48
4.096
2.50
±20
±30
6.5
200
-70
V
DD
+ 50mV
4.168
2.52
V
ppm/°C
k
µV
RMS
dB
V
Unipolar
V
IN
= V
DD
During acquisition time (Note 7)
0
±0.01
24
V
REF
±1
V
µA
pF
t
PU
t
ACQ
t
CONV
f
SCLK
Internally clocked
Externally clocked (Note 6)
Externally clocked conversion
Data I/O
30
< 50
2.7
0.1
4.8
10
External reference
Internal reference (Note 5)
0.6
3.5
0.8
65
µs
µs
µs
MHz
ns
ps
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX11618–MAX11621/MAX11624/MAX11625
40
100
µA
REF Input Current
I
REF
±0.1
±5
_______________________________________________________________________________________
3
10-Bit, 300ksps ADCs
with FIFO and Internal Reference
MAX11618–MAX11621/MAX11624/MAX11625
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 3.6V (MAX11619/MAX11621/MAX11625); V
DD
= 4.75V to 5.25V (MAX11618/MAX11620/MAX11624),
f
SAMPLE
= 300kHz, f
SCLK
= 4.8MHz (external clock, 50% duty cycle), V
REF
= 2.5V (MAX11619//MAX11621/MAX11625); V
REF
= 4.096V
(MAX11618/MAX11620/MAX11624), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MAX11618/MAX11620/MAX11624
MAX11619/MAX11621/MAX11625
MAX11618/MAX11620/MAX11624
MAX11619/MAX11621/MAX11625
V
IN
= 0V or V
DD
2.0
V
DD
x 0.7
200
±0.01
15
I
SINK
= 2mA
I
SINK
= 4mA
I
SOURCE
= 1.5mA
CS
= V
DD
CS
= V
DD
MAX11618/MAX11620/MAX11624
MAX11619/MAX11621/MAX11625
f
SAMPLE
= 300ksps
MAX11619/MAX11621/
MAX11625 Supply Current
(Note 9)
Internal reference
I
DD
External reference
f
SAMPLE
= 0, REF on
Shutdown
f
SAMPLE
= 300ksps
Shutdown
f
SAMPLE
= 300ksps
MAX11618/MAX11620/
MAX11624 Supply Current
(Note 9)
Internal reference
I
DD
External reference
Power-Supply Rejection
PSR
f
SAMPLE
= 0, REF on
Shutdown
f
SAMPLE
= 300ksps
Shutdown
4.75
2.7
1750
1000
0.2
1050
0.2
2300
1000
0.2
1550
0.2
±0.2
±0.2
V
DD
- 0.5
±0.05
15
5.25
3.6
2000
1200
5
1200
5
2550
1350
5
1700
5
±1
±1.4
mV
µA
µA
±1
0.4
0.8
±1.0
MIN
TYP
MAX
0.8
V
DD
x 0.3
UNITS
DIGITAL INPUTS (SCLK, DIN,
CS, CNVST)
(Note 8)
Input-Voltage Low
Input-Voltage High
Input Hysteresis
Input Leakage Current
Input Capacitance
DIGITAL OUTPUTS (DOUT,
EOC)
Output-Voltage Low
Output-Voltage High
Three-State Leakage Current
Three-State Output
POWER REQUIREMENTS
Supply Voltage
V
DD
V
V
OL
V
OH
I
L
C
OUT
V
V
µA
pF
V
IL
V
IH
V
HYST
I
IN
C
IN
V
V
mV
µA
pF
V
DD
= 2.7V to 3.6V, full-scale input
V
DD
= 4.75V to 5.25V, full-scale input
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Limits at T
A
= -40°C are guaranteed by design and not production tested.
MAX11619/MAX11621/MAX11625 tested at V
DD
= +3V. MAX11618/MAX11620/MAX11624 tested at V
DD
= +5V.
Offset nulled.
Time for reference to power up and settle to within 1 LSB.
Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
See Figure 3 (Equivalent Input Circuit) and the Sampling Error vs. Source Impedance curve in the
Typical Operating
Characteristics
section.
Note 8:
When
CNVST
is configured as a digital input, do not apply a voltage between V
IL
and V
IH
.
Note 9:
Supply current is specified depending on whether an internal or external reference is used for voltage conversions.
4
_______________________________________________________________________________________
10-Bit, 300ksps ADCs
with FIFO and Internal Reference
MAX11618–MAX11621/MAX11624/MAX11625
TIMING CHARACTERISTICS (Figure 1)
(V
DD
= 2.7V to 3.6V (MAX11619/MAX11621/MAX11625); V
DD
= 4.75V to 5.25V (MAX11618/MAX11620/MAX11624),
f
SAMPLE
= 300kHz, f
SCLK
= 4.8MHz (50% duty cycle), V
REF
= 2.5V (MAX11619/MAX11621/MAX11625); V
REF
= 4.096V
(MAX11618/MAX11620/MAX11624), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
SCLK Clock Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Fall to DOUT Transition
CS
Rise to DOUT Disable
CS
Fall to DOUT Enable
DIN to SCLK Rise Setup
SCLK Rise to DIN Hold
CS
Low to SCLK Setup
CS
High to SCLK Setup
CS
High After SCLK Hold
CS
Low After SCLK Hold
CNVST
Pulse Width Low
CS
or
CNVST
Rise to
EOC
Low (Note 10)
SYMBOL
t
CP
t
CH
t
CL
t
DOT
t
DOD
t
DOE
t
DS
t
DH
t
CSS0
t
CSS1
t
CSH1
t
CSH0
t
CSPW
CKSEL = 00
CKSEL = 01
Voltage conversion
Reference power-up
C
LOAD
= 30pF
C
LOAD
= 30pF
C
LOAD
= 30pF
40
0
40
40
0
0
40
1.4
7
65
4
Data I/O
CONDITIONS
Externally clocked conversion
MIN
208
100
40
40
40
40
40
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
µs
Note 10:
This time is defined as the number of clock cycles needed for conversion multiplied by the clock period. If the internal refer-
ence needs to be powered up, the total time is additive.
Typical Operating Characteristics
(V
DD
= 3V (MAX11619/MAX11621/MAX11625); V
DD
= 5V (MAX11618/MAX11620/MAX11624), f
SCLK
= 4.8MHz, C
LOAD
= 30pF,
T
A
= +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX11618 toc01
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX11618 toc02
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
0.4
0.3
0.2
DNL (LSB)
0.1
0
-0.1
-0.2
MAX11618/MAX11620/
MAX11624
f
SAMPLE
= 300ksps
0
256
512
768
1024
MAX11618 toc03
0.5
0.4
0.3
0.2
INL (LSB)
0.5
0.4
0.3
0.2
INL (LSB)
0.1
0
-0.1
-0.2
MAX11619/MAX11621/
MAX11625
f
SAMPLE
= 300ksps
0
256
512
768
0.5
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
256
512
768
1024
OUTPUT CODE (DECIMAL)
MAX11618/MAX11620/
MAX11624
f
SAMPLE
= 300ksps
-0.3
-0.4
-0.5
-0.3
-0.4
-0.5
1024
OUTPUT CODE (DECIMAL)
OUTPUT CODE (DECIMAL)
_______________________________________________________________________________________
5
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