DATASHEET
ISL8002, ISL8002A, ISL80019, ISL80019A
Compact Synchronous Buck Regulators
The ISL8002, ISL8002A, ISL80019 and ISL80019A are highly
efficient, monolithic, synchronous step-down DC/DC converters
that can deliver up to 2A of continuous output current from a 2.7V
to 5.5V input supply. They use peak current mode control
architecture to allow very low duty cycle operation. They operate
at either 1MHz or 2MHz switching frequency, thereby providing
superior transient response and allowing for the use of small
inductors. They also have excellent stability and provide both
internal and external compensation options.
The ISL8002, ISL8002A, ISL80019 and ISL80019A integrate
very low r
DS(ON)
MOSFETs in order to maximize efficiency. In
addition, since the high-side MOSFET is a PMOS, the need for a
Boot capacitor is eliminated, thereby reducing external
component count. They can operate at 100% duty cycle (at 1MHz)
with a dropout of 200mV at 2A output current.
These devices can be configured for either PFM (discontinuous
conduction) or PWM (continuous conduction) operation at light
load. PFM provides high efficiency by reducing switching losses at
light loads and PWM reduces noise susceptibility and RF
interference.
These devices are offered in a space saving 8 pin 2mmx2mm
TDFN lead free package with exposed pad for improved thermal
performance. The complete converter occupies less than
0.10in
2
area.
FN7888
Rev 4.00
July 31, 2014
Features
• V
IN
range 2.7V to 5.5V
• V
OUT
range is 0.6V to V
IN
• I
OUT
maximum is 1.5A or 2A (see
Table 1 on page 3)
• Switching frequency is 1MHz or 2MHz (see
Table 1 on page 3)
• Internal or external compensation option
• Selectable PFM or PWM operation option
• Overcurrent and short circuit protection
• Over-temperature/thermal protection
• V
IN
Undervoltage Lockout and V
OUT
Overvoltage Protection
• Up to 95% peak efficiency
Applications
• General purpose point of load DC/DC
• Set-top boxes and cable modems
• FPGA power
• DVD, HDD drives, LCD panels, TV
Related Literature
• See
AN1803,
“1.5A/2A Low Quiescent Current High
Efficiency Synchronous Buck Regulator”
ISL8002
VIN
GND
+2.7V …+5.5V 1
VIN
C1
22μF
2
EN
PHASE 8
PGND 7
L1
1.2μH
C5
22μF
C6
22μF
+1.8V/2A
VOUT
GND
100
90
EFFICIENCY (%)
80
70
60
50
EN
3
MODE
R1
+0.6V 200k 1%
FB 6
COMP 5
R2
100k 1%
PG
4
PG
PAD
9
V
O
-
R
1
= R
2
----------- –
1
VFB
FIGURE 1. TYPICAL APPLICATION CIRCUIT CONFIGURATION
(INTERNAL COMPENSATION OPTION)
(EQ. 1)
40
0.0
2.5V
OUT
1.8V
OUT
1.5V
OUT
1.2V
OUT
0.9V
OUT
0.8V
OUT
0.2
0.4
0.6
0.8 1.0 1.2 1.4
OUTPUT LOAD (A)
1.6
1.8
2.0
FIGURE 2. EFFICIENCY vs LOAD
F
SW
= 1MHz, V
IN
= 3.3V, MODE = PFM, T
A
= +25°C
FN7888 Rev 4.00
July 31, 2014
Page 1 of 23
ISL8002, ISL8002A, ISL80019, ISL80019A
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PFM Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short-Circuit Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable, Disable, and Soft-Start Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Discharge Mode (Soft-Stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100% Duty Cycle (1MHz Version). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal ShutDown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Derating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Inductor and Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
17
18
18
18
18
18
18
18
18
19
19
19
19
19
19
19
20
21
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
FN7888 Rev 4.00
July 31, 2014
Page 2 of 23
ISL8002, ISL8002A, ISL80019, ISL80019A
TABLE 1. SUMMARY OF KEY DIFFERENCES
PART#
ISL80019
ISL80019A
ISL8002
ISL8002A
I
OUT
(MAX)
(A)
1.5
1.5
2
2
F
SW
(MHz)
1
2
1
2
2.7 to 5.5
0.6 to 5.5
8 pin 2mmx2mm TDFN
V
IN
RANGE
(V)
V
OUT
RANGE
(V)
PACKAGE
SIZE
NOTE: In this datasheet, the parts in the table above are collectively called "device".
TABLE 2. COMPONENT VALUE SELECTION TABLE
V
OUT
(V)
0.8
1.2
1.5
1.8
2.5
3.3
C1
(µF)
22
22
22
22
22
22
C5, C6
(µF)
22
22
22
22
22
22
C4
(pF)
22
22
22
22
22
22
L1
(µH)
1.0~2.2
1.0~2.2
1.0~2.2
1.0~3.3
1.5~3.3
1.5~4.7
R1
(kΩ)
33
100
150
200
316
450
R2
(kΩ)
100
100
100
100
100
100
FN7888 Rev 4.00
July 31, 2014
Page 3 of 23
ISL8002, ISL8002A, ISL80019, ISL80019A
Pin Configuration
ISL8002, ISL8002A, ISL80019, ISL80019A
(8 LD 2x2 TDFN)
TOP VIEW
VIN
EN
MODE
PG
1
2
3
4
THERMAL
PAD
(GND)
PAD
PIN 9
8
7
6
5
PHASE
PGND
FB
COMP
Pin Descriptions
PIN #
1
PIN NAME
VIN
PIN DESCRIPTION
The input supply for the power stage of the PWM regulator and the source for the internal linear regulator that provides
bias for the IC. Place a minimum of 10µF ceramic capacitance from VIN to GND and as close as possible to the IC for
decoupling.
Device enable input. When the voltage on this pin rises above 1.4V, the device is enabled. The device is disabled when
the pin is pulled to ground. When the device is disabled, a 100Ω resistor discharges the output through the PHASE pin.
See
Figure 3, “FUNCTIONAL BLOCK DIAGRAM” on page 5
for details.
Mode selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or ground for PFM
mode. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state in case the MODE pin is left
floating, however, it is not recommended to leave this pin floating.
Power-good output is pulled to ground during the soft-start interval and also when the output voltage is below regulation
limits. There is an internal 5MΩ internal pull-up resistor on this pin.
COMP is the output of the error amplifier. When COMP is tied high to VIN, compensation is internal. When COMP is
connected with a series resistor and capacitor to GND, compensation is external. See
“Loop Compensation Design” on
page 20
for more detail.
Feedback pin for the regulator. FB is the negative input to the voltage loop error amplifier. The output voltage is set by
an external resistor divider connected to FB. In addition, the power-good PWM regulator’s power-good and undervoltage
protection circuits use FB to monitor the output voltage.
Power and analog ground connections. Connect directly to the board GROUND plane.
Power stage switching node for output voltage regulation. Connect to the output inductor. This pin is discharged by an
100Ω resistor when the device is disabled. See
Figure 3, “FUNCTIONAL BLOCK DIAGRAM” on page 5
for details.
2
EN
3
MODE
4
5
PG
COMP
6
FB
7
8
9
PGND
PHASE
THERMAL PAD Power ground. This thermal pad provides a return path for the power stage and switching currents, as-well-as a thermal
(T-PAD)
path for removing heat from the IC to the board. Place thermal vias to the PGND plane in this pad.
FN7888 Rev 4.00
July 31, 2014
Page 4 of 23
ISL8002, ISL8002A, ISL80019, ISL80019A
Functional Block Diagram
COMP
27pF
MODE
SOFT-
Soft
START
*
SHUTDOWN
200kΩ
+
BANDGAP
-
SHUTDOWN
3pF
FB
1.15*VREF
6kΩ
SLOPE
Slope
COMP
VIN
-
+
OV
OCP
0.85*VREF
VIN
+
5MΩ
PG
1ms
DELAY
0.3V
* By default, when COMP is tied to VIN, the voltage loop is internally compensated with the 27pF and 200kΩ RC network.
Please see "COMP" pin in the “Pin Descriptions” table on
Page 4
for more details.
FN7888 Rev 4.00
July 31, 2014
+
EN
VREF
OSCILLATOR
EAMP
+
COMP
-
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
HS DRIVER
P
PHASE
+
N
PGND
+
CSA
-
+
-
-
UV
SKIP
+
-
NEG CURRENT
SENSING
-
SCP
ZERO-CROSS
SENSING
+
100Ω
SHUTDOWN
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
Page 5 of 23
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