Programmable FemtoClock® NG
LVPECL Oscillator Replacement
83PN187I
Data Sheet
General Description
The 83PN187I is a programmable LVPECL synthesizer that is
“forward” footprint compatible with standard 5mm x 7mm oscillators.
The device uses IDT’s fourth generation FemtoClock
®
NG
technology for an optimum of high clock frequency and low phase
noise performance. Forward footprint compatibility means that a
board designed to accommodate the crystal oscillator interface and
the optional control pins is also fully compatible with a canned
oscillator footprint - the canned oscillator will drop onto the
10-VFQFN footprint for second sourcing purposes. This capability
provides designers with programability and lead time advantages of
silicon/crystal based solutions while maintaining compatibility with
industry standard 5mm x 7mm oscillator footprints for ease of supply
chain management. Oscillator-level performance is maintained with
IDT’s 4
th
Generation FemtoClock
®
NG PLL technology, which
delivers sub 0.5ps rms phase jitter.
The 83PN187I defaults to 150MHz using a 25MHz crystal with 2
programming pins floating (pulled down/pulled up with internal pullup
or pulldown resistors) but can also be set to 4 different frequency
multiplier settings to support a wide variety of applications. The
below table shows some of the more common application settings.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Fourth Generation FemtoClock
®
Next Generation (NG)
technology
Footprint compatible with 5mm x 7mm differential oscillators
One differential LVPECL output pair
Crystal oscillator interface can also be overdriven by a
single-ended reference clock
Output frequency range: 125MHz –187.5MHz
Crystal/input frequency: 25MHz, 12pF parallel resonant crystal
VCO range: 2GHz – 2.5GHz
Cycle-to-cycle jitter: 10ps (maximum), 3.3V±5%
RMS phase jitter @ 156.25MHz, 12kHz – 20MHz:
0.339ps (typical)
Full 3.3V or 2.5V operating supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Common Applications and Settings
FSEL[1:0]
00
01
10
11 (default)
XTAL (MHz)
25
25
25
25
Output Frequency (MHz)
156.25
187.5
125
150
Application(s)
XAUI, 10GigE
8Gig Fibre Channel
Ethernet
SAS, Embedded
Processor
Pin Assignment
FSEL 0
9
8
7
FSE L1
OE
1
RESERVED
2
10
V
CC
nQ
Q
Block Diagram
OE
XTAL_IN
OSC
XTAL_OUT
Pullup
V
EE
3
4
5
6
XTAL_OUT
PFD
&
FemtoClock® NG
VCO
÷N
Q
nQ
83PN187I
÷M
FSEL0
FSEL1
Pullup
Pullup
Control
Logic
10-Lead VFQFN
5mm x 7mm x 1mm package body
K Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision A March 4, 2016
XTAL_IN
83PN187I Data Sheet
Table 1. Pin Descriptions
Number
1
2
3
4,
5
6, 7
8
9
10
Name
OE
RESERVED
V
EE
XTAL_OUT
XTAL_IN
Q, nQ
V
CC
FSEL0
FSEL1
Input
Reserve
Power
Input
Output
Power
Input
Input
Pullup
Pullup
Type
Pullup
Description
Output enable. LVCMOS/LVTTL interface levels.
Reserved pin. Do not connect.
Negative supply pin.
Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output. This
oscillator interface can also be driven by a single-ended reference clock.
Differential output pair. LVPECL interface levels.
Power supply pin.
Output divider control inputs. Sets the output divider value to one of four values.
See Table 3. LVCMOS/LVTTL interface levels.
Output divider control inputs. Sets the output divider value to one of four values.
See Table 3. LVCMOS/LVTTL interface levels
NOTE:
Pullup
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
Function Table
Table 3. Divider Function Table
FSEL[1:0]
00
01
10
1 1 (default)
M Value
÷100
÷90
÷80
÷84
N Value
÷16
÷12
÷16
÷14
©2016 Integrated Device Technology, Inc
2
Revision A March 4, 2016
83PN187I Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, I
O
Continuos Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
3.63V
0V to 2V
-0.5V to V
CC
+ 0.5V
50mA
100mA
39.2C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
131
Units
V
mA
Table 4B. Power Supply DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
124
Units
V
mA
Table 4C. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.465V
V
CC
= 2.625V
Input Low Voltage
Input
High Current
Input
Low Current
OE,
FSEL[1:0]
OE,
FSEL[1:0]
V
CC
= 3.465V
V
CC
= 2.625V
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-150
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
5
Units
V
V
V
V
µA
µA
V
IL
I
IH
I
IL
©2016 Integrated Device Technology, Inc
3
Revision A March 4, 2016
83PN187I Data Sheet
Table 4D. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
– 1.3
V
CC
– 2.0
0.6
Typical
Maximum
V
CC
– 0.8
V
CC
– 1.6
1.0
Units
V
V
V
NOTE 1: Outputs termination with 50 to V
CC
– 2V.
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
Minimum
Typical
Fundamental
25
50
7
MHz
Maximum
Units
pF
©2016 Integrated Device Technology, Inc
4
Revision A March 4, 2016
83PN187I Data Sheet
AC Electrical Characteristics
Table 6A. AC Characteristics,
V
cc
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
MAX
Parameter
Output Frequency
156.25MHz,
Integration Range: 12kHz – 20MHz
RMS Phase Jitter (Random);
NOTE 1
187.5MHz,
Integration Range: 12kHz – 20MHz
125MHz,
Integration Range: 12kHz – 20MHz
150MHz,
Integration Range: 12kHz – 20MHz
tjit(cc)
t
R
/ t
F
odc
Cycle-to-Cycle Jitter; NOTE 2
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
100
49
Test Conditions
Minimum
1250
0.339
0.321
0.309
0.315
Typical
Maximum
187.5
0.5
0.5
0.5
0.5
10
350
51
Units
MHz
ps
ps
ps
ps
ps
ps
%
tjit(Ø)
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Refer to the Phase Noise plots.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
Table 6B. AC Characteristics,
V
cc
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
MAX
Parameter
Output Frequency
156.25MHz,
Integration Range: 12kHz – 20MHz
RMS Phase Jitter (Random);
NOTE 1
187.5MHz,
Integration Range: 12kHz – 20MHz
125MHz,
Integration Range: 12kHz – 20MHz
150MHz,
Integration Range: 12kHz – 20MHz
tjit(cc)
t
R
/ t
F
odc
Cycle-to-Cycle Jitter; NOTE 2
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
100
49
Test Conditions
Minimum
125
0.347
0.326
0.315
0.317
Typical
Maximum
187.5
0.5
0.5
0.5
0.5
20
350
51
Units
MHz
ps
ps
ps
ps
ps
ps
%
tjit(Ø)
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Refer to the Phase Noise plots.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc
5
Revision A March 4, 2016
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