TB6556FG
TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic
TB6556FG
3-Phase Full-Wave Sine-Wave PWM Brushless Motor Controller
The TB6556FG is designed for motor fan applications for three-phase brushless DC (BLDC) motors.
Features
Sine-wave PWM control
Built-in triangular-wave generator
(Carrier cycle = f
OSC
/252 (Hz))
Built-in lead angle control function (0° to 58° in 32 steps)
External setting/automatic internal setting
Built-in dead time function (setting 1.9
μs
or 3.8
μs)
Overcurrent protection signal input pin
Built-in regulator (V
refout
= 5 V (typ.), 30 mA (max))
Operating supply voltage range: V
CC
= 6 V to 10 V
Weight: 0.63 g (typ.)
1
2012-10-22
TB6556FG
Block Diagram
G
in
24
G
out
25
PH
26
LPF
27
LA
28
Upper limit
Filter
Lower limit
X
in
14
X
out
15
HU 21
HV 20
HW 19
V
e
2
V
CC
1
Regulator
Internal
Phase
reference matching
voltage
Position detector
Counter
Output
waveform
generator
Data
select
Phase V
Comparator
Setting
dead
time
System clock
generator
5-bit AD
Phase U
Comparator
9 U
6 X
8 V
5 Y
7 W
120°/180°
GND 13
V
refout
23
Power-on
reset
RES 11
I
dc
3
CW/CCW 18
SS 22
FG 17
REV 16
ST/SP
CW/CCW
Protection
ERR
&
GB
reset
FG
Rotating
direction
Comparator
PWM
HU
HV
HW
Charger
Switching
120°/180°
and
gate block
protection
on/off
4 Z
6-bit triangular
wave generator
UL
30
LL
29
Peak hold
+
10 T
d
Phase W
Comparator
12 OS
120°-
turn-on
matrix
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes.
2
2012-10-22
TB6556FG
Pin Description
Pin No.
21
20
19
18
Symbol
HU
HV
HW
CW/CCW
Description
Positional signal input pin U
Positional signal input pin V
Positional signal input pin W
Rotation direction signal input
pin
Reset-signal-input pin
Voltage command signal
Gain setting
L: Forward
H: Reverse
L: Reset (output is non-active)
operation/halt operation, also used for gate protection,
built-in pull-up resistor
With built-in pull-down resistor
I
dc
signal level at a gain that optimizes the LA
Connect the peak-hold capacitor and discharge resistor to GND, parallel
to each other
Connect the low-pass filter capacitor (built-in 100 kΩ resistor)
Sets 0° to 58° in 32 steps
Set lower limit for LA (LL = 0 V to 5.0 V)
Set upper limit for LA (UL = 0 V to 5.0 V)
L: Active LOW
H: Active HIGH
Inputs DC link current.
Reference voltage: 0.5 V
With built-in filter (
≈
1
μs),
built-in digital filter (
≈
1
μs)
With built-in feedback resistor
Outputs clock signal
Outputs reference voltage
signal
FG signal output pin
Reverse rotation detection
signal
Outputs turn-on signal
Outputs turn-on signal
Outputs turn-on signal
Select active HIGH or active LOW using the output logic select pin.
6
5
4
1
10
22
13
X
Y
Z
V
CC
T
d
SS
GND
Outputs turn-on signal
Outputs turn-on signal
Outputs turn-on signal
Power supply voltage pin
Inputs setting dead time
120°/180° select signal
Ground pin
V
CC
= 6 to 10 V
L: 3.8
μs,
H or OPEN: 1.9
μs
L: 120° turn-on mode, H or OPEN: 180° turn-on mode
―
5 V (typ.), 30 mA (max)
Outputs 3 PPR of positional signal
Detects reverse rotation.
When positional signal is HHH or LLL, gate block protection operates.
With built-in pull-up resistor, built-in digital filter (
≈
500 ns)
Remarks
11
2
24
25
26
27
28
29
30
12
RES
V
e
G
in
G
out
PH
LPF
LA
LL
UL
OS
Peak hold
RC low-pass filter
Lead angle setting signal
input pin
Lower limit for LA
Upper limit for LA
Inputs output logic select
signal
Inputs overcurrent protection
signal
Inputs clock signal
3
14
15
23
17
16
9
8
7
I
dc
X
in
X
out
V
refout
FG
REV
U
V
W
3
2012-10-22
TB6556FG
Input/Output Equivalent Circuits
Pin Description
Symbol
Input/Output Signal
Input/Output Internal Circuit
Digital
Positional signal input pin U
Positional signal input pin V
Positional signal input pin W
HU
HV
HW
With Schmitt trigger
Hysteresis 300 mV (typ.)
Digital filter: 500 ns (typ.)
L: 0.8 V (max)
H: V
refout
−
1 V (min)
V
refout
V
refout
200 kΩ
2.0 kΩ
V
refout
V
refout
2.0 kΩ
V
refout
V
refout
2.0 kΩ
V
refout
V
refout
200 kΩ
2.0 kΩ
V
CC
100
Ω
150 kΩ
100 kΩ
100 kΩ
Forward/reverse switching
input pin
CW/CCW
L: Forward (CW)
H: Reverse (CCW)
Digital
L: 0.8 V (max)
H: V
refout
−
1 V (min)
Reset input
L: Stops operation (reset)
H: Operates
RES
Digital
L: 0.8 V (max)
H: V
refout
−
1 V (min)
Digital
120°/180° select signal
SS
L: 120° turn-on mode
H: 180° turn-on mode
(OPEN)
With Schmitt trigger
Hysteresis: 300 mV (typ.)
L: 0.8 V (max)
H: V
refout
−
1 V (min)
Voltage command signal
1.0 V < V
e
≤
2.1 V
Refresh operation
(X, Y, Z pins: ON duty of
8%)
V
e
Analog
Input voltage range 0 to 5.4 V
Input voltage of 5.4 V or higher is
clipped to 5.4 V.
4
2012-10-22
TB6556FG
Pin Description
Symbol
Input/Output Signal
When LA is fixed externally, connect
LL to GND and UL to V
refout
, and then
input the setting voltage to the LA pin.
Lead angle setting signal
input pin
0 V: 0°
5 V: 58°
(5-bit AD)
LA
Input voltage of V
refout
or higher is
clipped to V
refout
.
When LA is fixed automatically, open
the LA pin. In this state, the LA pin is
used only for confirmation of LA width.
Input voltage range: 0 V to 5.0 V
(V
refout
)
100
Ω
200 kΩ
Input/Output Internal Circuit
V
CC
Automatic LA
circuit
V
CC
Non-inverted amplifier
25 dB (max)
G
out
output voltage
LOW: GND
HIGH: V
CC
−
1.7 V
V
CC
Gain setting signal input
(LA setting)
G
in
G
out
G
in
100
Ω
G
out
I
dc
To peak
hold circuit
V
CC
Connect the peak-hold capacitor and
discharge resistor to GND, parallel to
each other.
100 kΩ/0.1μF recommended
Peak hold
(LA setting)
PH
100
Ω
100
Ω
V
CC
Connect the low-pass filter capacitor
Built-in 100 kΩ (typ.) resistor
0.1μF recommended
Low-pass filter
(LA setting)
LPF
100 kΩ
100
Ω
V
CC
Clip lower limit for LA
LL = 0 V to 5.0 V
When LL
UL, LA is fixed at LL value.
Lower limit for LA
LL
100
Ω
5
2012-10-22
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
