It is recommended that an external 10K resistor is connected to this pin.
With this resistor, 1 = Signifies the VCO has locked onto the target frequency.
0 = Not locked to the designated M&N register pair target frequency.
3.3V power supply for analog PLL.
Ground for analog PLL.
2.5V power supply for output buffers.
Ground for output buffers.
3.3V power supply for oscillator.
Ground for oscillator.
3.3V power supply for core.
Ground for core.
3.3V power supply.
4
27, 23, 19
26, 22, 18
6
11
12
14
9
10
XOUT
CPUT[0:2]
CPUC[0:2]
FSEL
SDATA
SCLK
CPU_STOP#
ADDRSEL
LOCK
O
O
O
I, PU
VDD
250K
I/O
I
VDD
VDD
I, PU
VDD
250K
I, PD
VDD
250K
Open
Drain
PWR
GND
PWR
GND
PWR
GND
PWR
GND
PWR
VDD
16
15
28, 24, 20
25, 21, 17
2
5
7
8
13
VDDA
VSSA
VDDQ
VSSQ
VDDX
VSSX
VDDC
VSSC
VDD
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 1.
The block write and block read
protocol is outlined in
Table 2
while
Table 3
outlines the corre-
sponding byte write and byte read protocol. The Byte Count
value returned is 09h.
The slave receiver address is either D2 or D4, depending on
the state of the ADDRSEL pin.
Note:
1. Throughout this document logic 0 and logic 1 state signals are referenced. As a clarification it should be understood that 1 = high and 0 = low voltage levels. These
levels are defined in the DC Electrical Specifications of this data sheet.
........................ Document #: 38-07534 Rev. *F Page 2 of 13
CY28508
Table 1. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation
1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should
be ‘0000000’
Block Write Protocol
Description
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
‘00000000’ stands for block operation
Acknowledge from slave
Byte Count from master – 8 bits
Acknowledge from slave
Data byte 0 from master – 8 bits
Acknowledge from slave
Data byte 1 from master – 8 bits
Acknowledge from slave
Data bytes from master/Acknowledge
Data Byte N – 8 bits
Acknowledge from slave
Stop
Block Read Protocol
Description
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
‘00000000’ stands for block operation
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge
Data byte 0 from slave – 8 bits
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data byte N from slave – 8 bits
Not Acknowledge
Stop
Byte Read Protocol
Description
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation, bits[6:0]
of the command code represents the offset of
the byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Data byte from slave – 8 bits
Not Acknowledge
Stop
Table 2. Block Read and Block Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
....
....
....
....
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
....
....
....
....
Table 3. Byte Read and Byte Write Protocol
Bit
1
2:8
9
10
11:18
Byte Write Protocol
Description
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed
Acknowledge from slave
Data byte from master – 8 bits
Acknowledge from slave
Stop
Bit
1
2:8
9
10
11:18
19
20:27
28
29
19
20
21:27
28
29
30:37
38
39
........................ Document #: 38-07534 Rev. *F Page 3 of 13
CY28508
Serial Control Registers
Byte 0 : CPU Control Register
Bit
7
6
5
4
3
2
1
0
@Pup
HW
0
0
1
1
1
1
1
Name
LOCK
SS_ENABLE
SST1
SST0
REF
CPUT/C2
CPUT/C1
CPUT/C0
0 = disabled, 1 = enabled.
Select spread percentage 1. See
Table 4
Select spread percentage 0. See
Table 4
REF Output Enable
0 = Disabled (three-stated)), 1 = Enabled
CPU2 Output Enable
0 = Disabled (three-stated), 1 = Enabled
CPU1 Output Enable
0 = Disabled (three-stated), 1 = Enabled
CPU0 Output Enable
0 = Disabled (three-stated), 1 = Enabled
Description
Lock Detect: 0 = not at final frequency, 1 = VCO locked (read-only).
Table 4. Spread Spectrum Table
SST1 SST0
0
0
1
1
0
1
0
1
% Spread
0.125%
Center spread Lexmark profile
0.25%
Center spread Lexmark profile
0.5%
Center spread Lexmark profile
0.5%
Center spread Linear profile
Glitch-free operation for both enabling and disabling Spread
Spectrum. To achieve down spread operation, reprogram the
N register to drop the frequency by half the spread amount.
Byte 1: Dial-a-Frequency Control Register N0 [default = 112.35 MHz, N = 43d, ODSEL = 1]
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
1
0
1
0
1
1
Description
Test Mode: 0 = normal operation, 1 = phase-locked loop (PLL) bypass mode, when OD = 3 then /3, when
OD = 2 then /2.
N6, most significant bit (MSB).
N5
N4
N3
N2
N1
N0, least significant bit (LSB).
Byte 2: Dial-a-Frequency Control Register M0 [default = 112.35MHz, M = 49d, ODSEL = 1]
Bit
7
@Pup
0
Description
The charge pump current value during Smooth-Track can be programmed to normal mode (2xICP) by
setting this bit to “1.” The default value of “0” (1xICP) will program the charge pump current to half of normal
and will reduce the bandwidth and hence the slew rate.
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