DATASHEET
ISL6611A
Phase Doubler with Integrated Drivers and Phase Shedding Function
The ISL6611A utilizes Intersil’s proprietary Phase Doubler
scheme to modulate two-phase power trains with single
PWM input. It doubles the number of phases that Intersil’s
ISL63xx multiphase controllers can support. At the same
time, the PWM line can be pulled high to disable the
corresponding phase or higher phase(s) when the enable
pin (EN_PH) is pulled low. This simplifies the phase
shedding implementation. For layout simplicity and
improving system performance, the device integrates two 5V
drivers (ISL6609) and current balance function.
The ISL6611A is designed to minimize the number of analog
signals interfacing between the controller and drivers in high
phase count and scalable applications. The common COMP
signal, which is usually seen with conventional cascaded
configuration, is not required; this improves noise immunity
and simplifies the layout. Furthermore, the ISL6611A
provides low part count and a low cost advantage over the
conventional cascaded technique.
The IC is biased by a single low voltage supply (5V),
minimizing driver switching losses in high MOSFET gate
capacitance and high switching frequency applications.
Bootstrapping of the upper gate driver is implemented via an
internal low forward drop diode, reducing implementation
cost, complexity, and allowing the use of higher
performance, cost effective N-Channel MOSFETs. Adaptive
shoot-through protection is integrated to prevent both
MOSFETs from conducting simultaneously.
The ISL6611A features 4A typical sink current for the lower
gate driver, enhancing the lower MOSFET gate hold-down
capability during PHASE node rising edge, preventing power
loss caused by the self turn-on of the lower MOSFET due to
the high dV/dt of the switching node.
The ISL6611A also features an input that recognizes a
high-impedance state, working together with Intersil
multiphase PWM controllers to prevent negative transients
on the controlled output voltage when operation is
suspended. This feature eliminates the need for the Schottky
diode that may be utilized in a power system to protect the
load from negative output voltage damage.
In addition, the ISL6611A’s bootstrap function is designed to
prevent the BOOT capacitor from overcharging, should
excessively large negative swings occur at the transitions of
the PHASE node.
FN6881
Rev 1.00
August 28, 2012
Features
• Proprietary Phase Doubler Scheme with Phase Shedding
Function (Patent Pending)
- Enhanced Light to Full Load Efficiency
• Patented Current Balancing with r
DS(ON)
Current Sensing
and Adjustable Gain
• Quad MOSFET Drives for Two Synchronous Rectified
Bridge with Single PWM Input
• Channel Synchronization and Interleaving Options
• Adaptive Zero Shoot-Through Protection
• 0.4 On-Resistance and 4A Sink Current Capability
• 36V Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention (ISL6611A)
• Supports High Switching Frequency (Up to 1MHz)
- Fast Output Rise and Fall
• Tri-State PWM Input for Output Stage Shutdown
• Phase Enable Input and PWM Forced High Output to
Interface with Intersil’s Controller for Phase Shedding
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat
No Leads-Product Outline
- Near Chip-Scale Package Footprint; Improves PCB
Utilization, Thinner Profile
- Pb-Free (RoHS Compliant)
Applications
• High Current Low Voltage DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
• High Phase Count and Phase Shedding Applications
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
FN6881 Rev 1.00
August 28, 2012
Page 1 of 14
ISL6611A
Functional Pin Descriptions
PACKAGE
PIN #
1
2
3
4
5
6
7
8
9
10
PIN
SYMBOL
GND
LGATEA
PVCC
IGAIN
PGND
LGATEB
EN_PH
FUNCTION
Bias and reference ground. All signals are referenced to this node. It is also the return of the sample and hold of the
r
DS(ON)
current sensing circuits. Place a high quality low ESR ceramic capacitor from this pin to VCC.
Lower gate drive output of Channel A. Connect to gate of the low-side power N-Channel MOSFET.
This pin supplies power to both the lower and higher gate drives. Place a high quality low ESR ceramic capacitor from
this pin to PGND.
A resistor from this pin to GND sets the current balance gain. See “Current Balance and Maximum Frequency” on
page 11 for more details.
Power ground return of both low gate drivers. It is also the return of the phase node clamp circuits.
Lower gate drive output of Channel B. Connect to gate of the low-side power N-Channel MOSFET.
Driver Enable Input. A signal high input enables the driver at the PWM rising edge, a signal low input pulls PWM pin to
VCC at the PWM falling edge and then enters tri-state.
PHASEB Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel B. This pin
provides a return path for the upper gate drive.
UGATEB Upper gate drive output of Channel B. Connect to gate of high-side power N-Channel MOSFET.
BOOTB
Floating bootstrap supply pin for the upper gate drive of Channel B. Connect the bootstrap capacitor between this pin
and the PHASEB pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See“Bootstrap
Considerations” on page 9 for guidance in choosing the capacitor value.
Floating bootstrap supply pin for the upper gate drive of Channel A. Connect the bootstrap capacitor between this pin
and the PHASEA pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Bootstrap
Considerations” on page 9 for guidance in choosing the capacitor value.
11
BOOTA
12
13
14
15
UGATEA Upper gate drive output of Channel A. Connect to gate of high-side power N-Channel MOSFET.
PHASEA Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel A. This pin
provides a return path for the upper gate drive.
VCC
PWM
Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR ceramic
capacitor from this pin to GND.
The PWM input signal triggers the J-K flip flop and alternates its input to channel A and B. Both channels are effectively
modulated. The PWM signal can enter three distinct states during operation, see “Tri-State PWM Input” on page 9 for
further details. Connect this pin to the PWM output of the controller. The pin is pulled to VCC when EN_PH is low and
the PWM input starts transitioning low.
A signal high synchronizes both channels with no phase shifted. A signal low interleaves both channels with 180°
out-of-phase.
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
16
17
SYNC
PAD
FN6881 Rev 1.00
August 28, 2012
Page 4 of 14
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