Si5310
P
RECISION
C
L O C K
M
ULTIPLIER
/ R
EGENERATOR
IC
Features
Complete precision clock multiplier and clock regenerator device:
Performs clock multiplication to one
of two frequency ranges:
150–167 MHz or 600–668 MHz
Jitter generation as low as
0.5 ps
rms
for 622 MHz output
Accepts input clock from
9.4–668 MHz
Regenerates a “clean”, jitter-
attenuated version of input clock
DSPLL™ technology provides
superior jitter performance
Small footprint: 4 x 4 mm
Low power: 310 mW typical
ROHS-compliant Pb-free
packaging option available
Ordering Information:
See page 21.
Applications
SONET/SDH systems
Terabit routers
Digital cross connects
Optical transceiver modules
Gigabit Ethernet systems
Fibre channel
Pin Assignments
Si5310
MULTOUT+
MULTOUT–
15
MULTSEL
Description
REXT
1
2
3
4
5
20 19 18 17 16
PWRDN
VDD
CLKOUT+
CLKOUT–
VDD
The Si5310 is a fully integrated low-power clock multiplier and clock
regenerator IC. The clock multiplier generates an output clock that is an
integer multiple of the input clock. The clock regenerator operates
simultaneously, creating a “clean” version of the input clock by using the
clock synthesis phase-locked loop (PLL) to remove unwanted jitter and
square up the input clock’s rising and falling edges. The Si5310 uses
Silicon Laboratories patented DSPLL
®
architecture to achieve superior
jitter performance while eliminating the analog loop filter found in
traditional PLL designs with a digital signal-processing algorithm.
The Si5310 represents a new standard in low jitter, small size, low power,
and ease-of-use for clock devices. It operates from a single 2.5 V supply
over the industrial temperature range (–40 to 85 °C).
VDD
GND
REFCLK+
REFCLK–
GND
NC
GND
Pad
14
13
12
11
6
LOL
7
VDD
8
GND
9
CLKIN+
10
CLKIN–
Functional Block Diagram
Regeneration
BUF
2
CLKOUT+
CLKOUT–
CLKIN+
CLKIN–
2
BUF
DSPLL
®
Phase-Locked
Loop
Calibration
2
PWRDN/CAL
MULTOUT+
MULTOUT–
LOL
BUF
2
Bias Gen
REFCLK+
REFCLK–
MULTSEL
REXT
Rev. 1.3 6/08
Copyright © 2008 by Silicon Laboratories
Si5310
Si5310
T
ABLE
Section
OF
C
ONTENTS
Page
1. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1. DSPLL® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2. Clock Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3. 1x Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4. Clock Regeneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.6. DSPLL Lock Detection (Loss-of-Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.7. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.8. Device Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.9. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.10. Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.11. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.12. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.13. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5. Pin Descriptions: Si5310 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7. Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9. 4x4 mm 20L QFN Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Rev. 1.3
3
Si5310
1. Detailed Block Diagram
Regen
Retime
CLKOUT+
CLKOUT–
c
CLKIN+
CLKIN–
Phase
Detector
A/D
DSP
n
VCO
CLK
Divider
MULTOUT+
c
MULTOUT–
REFCLK+
REFCLK–
Lock
Detector
LOL
MULTSEL
REXT
Bias
Generation
Calibration
PWRDN/CAL
4
Rev. 1.3
Si5310
2. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Si5310 Supply Voltage
2
Symbol
T
A
V
DD
Test Condition
Min
1
–40
2.375
Typ
25
2.5
Max
1
85
2.625
Unit
°C
V
Notes:
1.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
2.
The Si5310 specifications are guaranteed when using the recommended application circuit (including component
tolerance) of "3. Typical Application Circuit" on page 11.
V
SIG NAL +
Differential
V
ICM
, V
O CM
SIG NAL –
I/Os
V
IS
(SIGNAL +) – (SIGNAL –)
Differential
Voltage Swing
V
ID
,V
O D
Differential Peak-to-Peak Voltage
t
Figure 1. Differential Voltage Measurement (CLKIN, REFCLK, CLKOUT, MULTOUT)
CLKIN
MULTOUT
t
CI-M
t
M-CO
1/f
MULT
CLKOUT
Figure 2. CLKIN to CLKOUT, MULTOUT Phase Relationship
CLKIN,
REFCLK,
CLKOUT,
MULTOUT
80%
20%
t
F
t
R
Figure 3. Differential Clock Input and Output Rise/Fall Times
Rev. 1.3
5
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