128K X 36, 3.3V Synchronous
IDT71V547S/XS
SRAM with ZBT™ Feature, Burst
Counter and Flow-Through Outputs
Features
◆
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◆
◆
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128K x 36 memory configuration, flow-through outputs
Supports high performance system speed - 95 MHz
(8ns Clock-to-Data Access)
ZBT
TM
Feature - No dead cycles between write and read
cycles
Internally synchronized signal eliminates the need to
control
OE
Single R/W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
Individual byte write (BW
1
-
BW
4
) control (May tie active)
Three chip enables for simple depth expansion
Single 3.3V power supply (±5%)
Packaged in a JEDEC standard 100-pin TQFP package
Functional Block Diagram
LBO
Address A [0:16]
CE1,
CE2,
CE2
R/W
CEN
ADV/LD
BWx
Input Register
128K x 36 BIT
MEMORY ARRAY
D
Q
Address
D
Q
Control
DI
DO
D
Clk
Q
Control Logic
Mux
Clock
Sel
OE
Gate
,
Data I/O [0:31], I/O P[1:4]
3822 drw 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
FEBRUARY 2015
DSC-3822/07
1
©2015 Integrated Device Technology, Inc.
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
The IDT71V547 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM organized as 128K x 36 bits. It is designed to eliminate
dead bus cycles when turning the bus around between reads and writes,
or writes and reads. Thus it has been given the name ZBT
TM
, or Zero Bus
Turn-around.
Address and control signals are applied to the SRAM during one clock
cycle, and on the next clock cycle, its associated data cycle occurs, be it
read or write.
The IDT71V547 contains address, data-in and control signal regis-
ters. The outputs are flow-through (no output data register). Output enable
is the only asynchronous signal and can be used to disable the outputs at
any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V547 to
be suspended as long as necessary. All synchronous inputs are
ignored when
CEN
is high and the internal device registers will hold
their previous values.
Description
There are three chip enable pins (CE
1
, CE
2
,
CE
2
) that allow the user
to deselect the device when desired. If any one of these three is not active
when ADV/LD is low, no new memory operation can be initiated and any
burst in progress is stopped. However, any pending data transfers (reads
or writes) will be completed. The data bus will tri-state one cycle after the
chip was deselected or write initiated.
The IDT71V547 has an on-chip burst counter. In the burst mode, the
IDT71V547 can provide four cycles of data for a single address presented
to the SRAM. The order of the burst sequence is defined by the
LBO
input
pin. The
LBO
pin selects between linear and interleaved burst sequence.
The ADV/LD signal is used to load a new external address (ADV/LD =
LOW) or increment the internal burst counter (ADV/LD = HIGH).
The IDT71V547 SRAM utilizes IDT's high-performance, high-volume
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x
20mm 100-pin thin plastic quad flatpack (TQFP) for high board density.
Pin Description Summary
A
0
- A
16
CE
1
, CE
2
,
CE
2
OE
R/W
CEN
BW
1
,
BW
2
,
BW
3
,
BW
4
CLK
ADV/LD
LBO
I/O
0
- I/O
31
, I/O
P1
- I/O
P4
V
DD
V
SS
Address Inputs
Three Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance Burst Address / Load New Address
Linear / Interleaved Burst Order
Data Input/Output
3.3V Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Static
Static
3822 tbl 01
2
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions
(1)
Symbol
A
0
- A
16
Pin Function
Address Inputs
I/O
I
Active
N/A
Description
Synchronous Address inputs. The address register is triggered by a combination
of the rising edge of CLK, ADV/LD Low,
CEN
Low and true chip enables.
ADV/LD is a synchronous input that is used to load the internal registers with new
address and control when it is sampled low at the rising edge of clock with the
chip selected. When ADV/LD is low with the chip deselected, any burst in
progress is terminated. When ADV/LD is sampled high then the internal burst
counter is advanced for any burst that was in progress. The external addresses
are ignored when ADV/LD is sampled high.
R/W signal is a synchronous input that identifies whether the current load cycle
initiated is a Read or Write access to the memory array. The data bus activity for
the current cycle takes place one clock cycle later.
Synchronous Clock Enable Input. When
CEN
is sampled high, all other
synchronous inputs, including clock are ignored and outputs remain unchanged.
The effect of
CEN
sampled high on the device outputs is as if the low to high
clock transition did not occur. For normal operation,
CEN
must be sampled low at
rising edge of clock.
Synchronous byte write enables. Enable 9-bit byte has its own active low byte
write enable. On load write cycles (When R/W and ADV/LD are sampled low) the
appropriate byte write signal (BW
1
-
BW
4
) must be valid. The byte write signal
must also be valid on each cycle of a burst write. Byte Write signals are ignored
when R/W is sampled high. The appropriate byte(s) of data are written into the
device one cycle later.
BW
1
-
BW
4
can all be tied low if always doing write to the
entire 36-bit word.
Synchronous active low chip enable.
CE
1
and
CE
2
are used with CE
2
to
enable the IDT71V547. (CE
1
or
CE
2
sampled high or CE
2
sampled low) and
ADV/LD low at the rising edge of clock, initiates a deselect cycle. This device has
a one cycle deselect, i.e., the data bus will tri-state one clock cycle after deselect
is initiated.
Synchronout active high chip enable. CE
2
is used with
CE
1
and
CE
2
to enable
the chip. CE
2
has inverted polarity but otherwise identical to
CE
1
and
CE
2
.
This is the clock input to the IDT71V547. Except for
OE,
all timing references for
the device are made with respect to the rising edge of CLK.
Data input/output (I/O) pins. The data input path is registered, triggered by the
rising edge of CLK. The data output path is flow-through (no output register).
Burst order selection input. When
LBO
is high the Interleaved burst sequence is
selected. When
LBO
is low the Linear burst sequence is selected.
LBO
is a static
DC input.
Asynchronous output enable.
OE
must be low to read data from the 71V547.
When
OE
is high the I/O pins are in a high-impedance state.
OE
does not need
to be actively controlled for read and write cycles. In normal operation,
OE
can be
tied low.
3.3V power supply input.
Ground pin.
3822 tbl 02
ADV/LD
Address/Load
I
N/A
R/W
Read/Write
I
N/A
CEN
Clock Enable
I
LOW
BW
1
-
BW
4
Individual Byte
Write Enables
I
LOW
CE
1
,
CE
2
Chip Enables
I
LOW
CE2
CLK
I/O
0
- I/O
31
I/O
P1 -
I/O
P4
LBO
Chip Enable
Clock
Data Input/Output
Linear Burst
Order
Output Enable
I
I
I/O
I
HIGH
N/A
N/A
LOW
OE
I
LOW
V
DD
V
SS
Power Supply
Ground
N/A
N/A
N/A
N/A
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
3
6.42
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
V
SS
0V
0V
V
DD
3.3V±5%
3.3V±5%
3822 tbl 03
Recommended DC Operating
Conditions
Symbol
V
DD
V
SS
V
IH
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
Min.
3.135
0
2.0
2.0
-0.5
(1)
Typ.
3.3
0
____
____
____
Max.
3.465
0
4.6
V
DD
+0.3
(2)
0.8
Unit
V
V
V
V
V
3822 tbl 04
NOTES:
1. V
IL
(min.) = –1.0V for pulse width less than t
CYC
/2, once per cycle.
2. V
IH
(max.) = +6.0V for pulse width less than t
CYC
/2, once per cycle.
Capacitance
Symbol
C
IN
C
I/O
(T
A
= +25°C, f = 1.0MHz, TQFP package)
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
5
7
Unit
pF
pF
3822 tbl 06
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Supply Voltage on VDD with
Respect to GND
DC Input Voltage
(5)
DC Voltage Applied to Outputs in
High-Z State
(5)
Operating Temperature
Ambient Temperature with Power
Applied (Temperature Under
Bias)
Storage Temperature
Current into Outputs (Low)
Static Discharge Voltage
(per MIL-STD-883, Method 3015)
Latch-Up Current
Value
–0.5 to +3.6
–0.5 to V
DDQ
+0.5
–0.5 to V
DDQ
+0.5
0°C to 70°C
–55 to +125
Unit
V
V
V
°C
°C
V
TERM
(3)
V
TERM
(4)
T
A
T
BIAS
T
STG
I
OUT
V
ESD
I
LU
–65 to +150
20
>2001
>200
°C
mA
V
mA
NOTES:
5284 tbl 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. V
DD
and Input terminals only.
3. I/O terminals.
4
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/O
P3
I/O
1
6
I/O
1
7 DD
V
V
SS
I/O
1
8
I/O
1
9
I/O
20
I/O
21
V
SS
V
DD
I/O
22
I/O
23
V
SS
(1)
V
DD
V
DD
V
SS
I/O
24
I/O
25
V
DD
V
SS
I/O
26
I/O
27
I/O
28
I/O
29
V
SS
V
DD
I/O
30
I/O
31
I/O
P4
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
NC
(2)
A
8
A
9
A
6
A
7
CE
1
CE
2
BW
4
BW
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PK100
I/O
P2
I/O
15
I/O
14
V
DD
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DD
I/O
9
I/O
8
V
SS
V
SS
V
DD
V
SS
I/O
7
I/O
6
V
DD
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DD
I/O
1
I/O
0
I/O
P1
LBO
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
A
15
A
16
Top View
TQFP
3822 drw 02
NOTES:
1. Pin 14 does not have to be connected directly to V
SS
as long as the input voltage is < V
IL
.
2. Pins 83 and 84 are reserved for future A
17
(8M) and A
18
(16M) respectively.
5
6.42
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