MAX121C_ ..........................................................0°C to +70°C
MAX121E_ ...................................................... -40°C to +85°C
Storage Temperature Range ........................... -65°C to + 160°C
Lead Temperature (soldering, 10s) ................................. +300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(V
DD
= 4.75V to 5.25V, V
SS
= -10.8V to -15.75V, f
CLK
= 5.5MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MAX121C
MAX121E
MIN
75
73
77
14
12 bits no missing codes over temperature
range
Code 00..00 to 00..01 transition,
near V
AIN
= 0V
Temperature drift
Full-Scale Error (Notes 1, 2)
Full-Scale Temperature Drift
Power-Supply Rejection
ANALOG INPUT
Input Range
Input Current
Input Capacitance (Note 3)
Full-Power Bandwidth
1.5
V
AIN
= 5V (R
IN
approximately 6kW to REF)
-5
+5
2.5
10
V
mA
pF
MHz
Including reference; adjusted for bipolar
zero error; T
A
= +25°C
Excluding reference
V
DD
only, 5V
±5%
V
SS
only, -12V
±10%
V
SS
only, -15V
±5%
±1
±1/2
±1
±1
±2
±2
±2
LSB
±1
±0.2
±1.5
±2
±10
TYP
78
77
-85
86
-77
MAX
UNITS
DYNAMIC PERFORMANCE (f
S = 308kHz, VAIN = 10VP-P, 50kHz)
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
ACCURACY
Resolution
Differential Nonlinearity (Note 1)
Integral Nonlinearity
Bipolar Zero Error
RES
DNL
INL
Bits
LSB
LSB
mV
ppm/°C
%
ppm/°C
SINAD
THD
SFDR
Including distortion
First five harmonics
dB
dB
dB
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Maxim Integrated
│
2
MAX121
308ksps ADC with DSP Interface and 78dB SINAD
Electrical Characteristics (continued)
(V
DD
= 4.75V to 5.25V, V
SS
= -10.8V to -15.75V, f
CLK
= 5.5MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
REFERENCE
Output Voltage
External Load Regulation
Temperature Drift (Note 4)
CONVERSION TIME
Synchronous
Clock Frequency
t
CONV
f
CLK
SYMBOL
CONDITIONS
No external load, V
AIN
= 5V, T
A
= +25°C
0mA < I
SINK
< 5mA, V
AIN
= 0V
MIN
-5.02
TYP
MAX
-4.98
5
±30
UNITS
V
mV
ppm/°C
µs
MHz
V
16 t
CLK
0.1
2.4
2.91
5.5
DIGITAL INPUTS (CLKIN,
CONVST, CS)
Input High Voltage
Input Low Voltage
Input Capacitance (Note 3)
Input Current
Output Low Voltage
Output High Voltage
Leakage Current
Output Capacitance (Note 3)
POWER REQUIREMENTS
Positive Supply Voltage
Negative Supply Voltage
Positive Supply Current
Negative Supply Current
Power Dissipation
V
IH
V
IL
V
DD
= 0V or VDD
V
OL
V
OH
I
LKG
0.8
10
±5
0.4
V
DD
- 0.5
±5
10
V
pF
µA
V
V
µA
pF
V
V
mA
mA
mW
DIGITAL OUTPUTS (SCLK, SDATA, FSTRT, SFRM)
I
SINK
= 1.6mA
I
SOURCE
= 1mA
V
OUT
= 0V or V
DD
V
DD
V
SS
I
DD
I
SS
By supply rejection test
By supply rejection test
V
DD
= 15.25V, V
SS
= -15.75V, V
AIN
= 0V,
V
CS
= V
CONVST
= V
MODE
= 5V
V
DD
= 15.25V, V
SS
= -15.75V, V
AIN
= 0V,
V
CS
= V
CONVST
= V
MODE
= 5V
V
DD
= 15.25V, V
SS
= 12V, V
AIN
= 0V,
V
CS
= V
CONVST
= V
MODE
= 5V
4.75
-10.8
9
14
213
5.25
-15.75
15
20
315
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Maxim Integrated
│
3
MAX121
308ksps ADC with DSP Interface and 78dB SINAD
Timing Characteristics
(V
DD
= 5V, V
SS
= -12V or -15V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 5)
PARAMETER
CONVST
Pulse
Width (Note 6)
Data-Access Time
Data-Hold Time
CLKIN to SCLK
SCLK to SDATA
Skew
SCLK to SFRM or
FSTRT Skew
Acquisition Time
(Note 6)
Aperture Delay
Aperture Jitter
Clock Setup/Hold
Time
Note
Note
Note
Note
1:
2:
3:
4:
tCK
10
SYMBOL CONDITIONS
tCW
tDA
tDH
tCD
tSC
tSC
tAQ
tAP
CL = 50pF
CL = 50pF
CL = 50pF
CL = 50pF
400
10
30
50
10
50
10
50
TA = +25°C
MIN TYP
MAX
20
25
25
40
50
50
65
±65
±25
400
MAX121C/E
MIN
30
65
65
85
±80
±35
400
TYP
MAX
MIN
35
80
80
105
±100
±40
MAX121M
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
These tests are performed at V
DD
= +5V. V
SS
= -15V. Operation over supply is guaranteed by supply-rejection tests.
Ideal full-scale transition is at +5V - 3/2 LSB = +4.9991V adjusted for offset error.
Guaranteed, not tested.
Temperature drift is defined as the change in output voltage from +25°C to T
MIN
or T
MAX
. It is calculated as
T
C
= (ΔV
REF
/V
REF
)/ΔT.
Note 5:
Control inputs specified with t
r
= t
f
= 5ns (10% to 90% of +5V) and timed from a voltage level of 1.6V. Output delays are
measured to +0.8V if going low, or +2.4V if going high. For a data-hold time, a change of 0.5V is measured. See Figures 4
and 5 for load circuits.
Note 6:
Guaranteed, not tested.
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Maxim Integrated
│
4
MAX121
308ksps ADC with DSP Interface and 78dB SINAD
Pin Configurations
TOP VIEW
1
2
3
4
5
6
7
8
+
V
SS
V
DD
AIN
MODE
16
15
14
13
12
11
10
9
V
SS
V
DD
AIN
V
REF
N.C.
N.C.
AGND
INVCLK
INVFRM
1
2
3
4
5
6
7
8
9
+
20 MODE
19 CS
18 CLKIN
17 CONVST
16 N.C.
15 N.C.
14 SCLK
13 SDATA
12 FSTRT
11 SFRM
MAX121
CS
CLKIN
MAX121
V
REF
AGND
INVCLK
INVFRM
DGND
CONVST
SCLK
SDATA
FSTRT
SFRM
DGND 10
SSOP
PDIP/SO
Pin Description
PIN
PDIP/SO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
—
SSOP
1
2
3
4
7
8
9
10
11
12
13
14
17
18
19
20
5, 6, 15, 16
NAME
VSS
VDD
AIN
VREF
AGND
INVCLK
INVFRM
DGND
SFRM
FSTRT
SDATA
SCLK
CONVST
CLKIN
CS
MODE
N.C.
FUNCTION
Negative Power Supply, -12V or -15V. Bypass to AGND with 10µF and 0.1µF capacitors.
Positive Power Supply, +5V. Bypass to AGND with 10µF and 0.1µF capacitors.
Sampling Analog Input, ±5V Bipolar Input Range
-5V Reference Output. Bypass to AGND with 22µF || 0.1µF capacitors.
Analog Ground
Invert Serial Clock. Connect to DGND to invert the SCLK output (relative to CLKIN).
Invert Serial Frame. This input sets the polarity of the SFRM output as follows:
If
INVFRM
= DGND, SFRM is high during a conversion.
If
INVFRM
= VDD, SFRM is low during a conversion.
Digital Ground
Serial Frame Output. Normally high (INVFRM = VDD), falls at the beginning of the
conversion and rises at the end (after 16 tCLK) signaling the end of a 16-bit frame.
Frame Start Output. High pulse that lasts one clock cycle, falling edge indicates that a valid
MSB is available.
Serial Data Output. MSB first, two’s-complement binary output code.
Serial Clock Output. Same polarity as CLKIN if
INVCLK
= VDD, inverted CLKIN if
INVCLK
= DGND. Note that SCLK runs whenever CLKIN is active.
Active-Low Convert Start Input. Conversions are initiated on falling edges.
Clock Input. Supply at TTL-/CMOS-compatible clock from 0.1MHz to 5.5MHz, 40% to 60%
duty cycle.
Active-Low Chip Select Input.
CS
= DGND enables the three-state outputs. Also, if
CONVST
is low, initiates a conversion on the falling edge of
CS.
Hardwire to set operational mode. VDD (single conversions),
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