CY7C1366C
CY7C1367C
9-Mbit (256K × 36/512K × 18)
Pipelined DCD Sync SRAM
9-Mbit (256K × 36/512K × 18) Pipelined DCD Sync SRAM
Features
■
■
■
Supports bus operation up to 166 MHz
Available speed grade is 166 MHz
Registered inputs and outputs for pipelined operation
❐
Optimal for performance (double-cycle deselect)
• Depth expansion without wait state
❐
3.3 V – 5% and + 10% core power supply (V
DD
)
2.5 V/3.3 V I/O power supply (V
DDQ
)
Fast clock-to-output times
❐
3.5 ns (for 166 MHz device)
Provide high performance 3-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Available in Pb-free 100-pin TQFP and non Pb-free 119-ball
BGA package
IEEE 1149.1 JTAG-compatible boundary scan
“ZZ” sleep mode option
circuitry and a two-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
chip enable (CE
1
), depth-expansion chip enables (CE
2
and
CE
3[1]
), burst control inputs (ADSC, ADSP, and ADV), write
enables (BW
X
, and BWE), and global write (GW). Asynchronous
inputs include the output enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see
Pin Definitions on page 6
and
Partial Truth Table
for Read/Write on page 9
for further details). Write cycles can be
one to four bytes wide as controlled by the byte write control
inputs. GW active LOW causes all bytes to be written. This
device incorporates an additional pipelined enable register which
delays turning off the output buffers an additional cycle when a
deselect is executed. This feature enables depth expansion
without penalizing system performance.
The CY7C1366C/CY7C1367C operates from a +3.3 V core
power supply while all outputs operate with a +3.3 V or a +2.5 V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click
here.
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■
■
■
■
■
■
■
■
■
Functional Description
The CY7C1366C/CY7C1367C SRAM integrates 256K × 36 and
512K × 18 SRAM cells with advanced synchronous peripheral
Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
166 MHz
3.5
180
40
Unit
ns
mA
mA
Note
1. CE
3
is for 100-pin TQFP. 119-ball BGA is offered only in 2 Chip Enable.
Cypress Semiconductor Corporation
Document Number: 38-05542 Rev. *N
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 12, 2018
CY7C1366C
CY7C1367C
Logic Block Diagram – CY7C1366C
A 0,A1,A
ADDRESS
REGISTER
2 A[1:0]
MODE
ADV
CLK
BURST
LOGIC
Q1
COUNTER AND
CLR
ADSC
ADSP
BW
D
DQ
D,
DQP
D
BYTE
WRITE REGISTER
DQ
c
,DQP
C
BYTE
WRITE REGISTER
DQ
B
,DQP
B
BYTE
WRITE REGISTER
DQ
A,
DQP
A
BYTE
WRITE REGISTER
ENABLE
REGISTER
Q0
DQ
D,
DQP
D
BYTE
WRITE DRIVER
DQ
c
,DQP
C
BYTE
WRITE DRIVER
DQ
B
,DQP
B
BYTE
WRITE DRIVER
DQ
A,
DQP
A
BYTE
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
BW
C
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
BW
B
DQs
DQP
A
DQP
B
DQP
C
DQP
D
BW
A
BWE
GW
CE
1
CE
2
CE
3
OE
PIPELINED
ENABLE
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Logic Block Diagram – CY7C1367C
A 0, A1, A
ADDRESS
REGISTER
2
A
[1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
B,
DQP
B
BYTE
WRITE REGISTER
DQ
A ,
DQP
A
BYTE
WRITE REGISTER
ENABLE
REGISTER
DQ
B ,
DQP
B
BYTE
WRITE DRIVER
DQ
A,
DQP
A
BYTE
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
BW
B
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQ
s,
DQP
A
DQP
B
BW
A
BWE
GW
CE
1
CE
2
CE
3
OE
PIPELINED
ENABLE
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Document Number: 38-05542 Rev. *N
Page 2 of 32
CY7C1366C
CY7C1367C
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 7
Single Read Accesses ................................................ 7
Single Write Accesses Initiated by ADSP ................... 8
Single Write Accesses Initiated by ADSC ................... 8
Burst Sequences ......................................................... 8
Sleep Mode ................................................................. 8
Interleaved Burst Address Table ................................. 8
Linear Burst Address Table ......................................... 8
ZZ Mode Electrical Characteristics .............................. 8
Partial Truth Table for Read/Write .................................. 9
Partial Truth Table for Read/Write .................................. 9
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 10
Disabling the JTAG Feature ...................................... 10
Test Access Port (TAP) ............................................. 10
PERFORMING A TAP RESET .................................. 10
TAP REGISTERS ...................................................... 10
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 12
TAP Controller Block Diagram ...................................... 13
TAP Timing ...................................................................... 13
TAP AC Switching Characteristics ............................... 14
3.3 V TAP AC Test Conditions ....................................... 14
3.3 V TAP AC Output Load Equivalent ......................... 14
2.5 V TAP AC Test Conditions ....................................... 14
2.5 V TAP AC Output Load Equivalent ......................... 14
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 15
Identification Register Definitions ................................ 16
Scan Register Sizes ....................................................... 16
Identification Codes ....................................................... 16
Boundary Scan Order .................................................... 17
Maximum Ratings ........................................................... 18
Operating Range ............................................................. 18
Neutron Soft Error Immunity ......................................... 18
Electrical Characteristics ............................................... 18
Capacitance .................................................................... 19
Thermal Resistance ........................................................ 19
AC Test Loads and Waveforms ..................................... 20
Switching Characteristics .............................................. 21
Switching Waveforms .................................................... 22
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagrams .......................................................... 27
Acronyms ........................................................................ 28
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC® Solutions ...................................................... 32
Cypress Developer Community ................................. 32
Technical Support ..................................................... 32
Document Number: 38-05542 Rev. *N
Page 3 of 32
CY7C1366C
CY7C1367C
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3 Chip Enables)
A
A
CE
1
CE
2
BW
D
BW
C
BW
B
BW
A
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DQP
C
DQ
C
DQ
C
V
DDQ
V
SSQ
DQ
C
DQ
C
DQ
C
DQ
C
V
SSQ
V
DDQ
DQ
C
DQ
C
NC
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SSQ
DQ
D
DQ
D
DQ
D
DQ
D
V
SSQ
V
DDQ
DQ
D
DQ
D
DQP
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1366C
(256K × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQP
B
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SSQ
DQ
A
DQ
A
DQ
A
DQ
A
V
SSQ
V
DDQ
DQ
A
DQ
A
DQP
A
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
NC
V
DD
NC
V
SS
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQP
B
NC
V
SSQ
V
DDQ
NC
NC
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE
1
CE
2
NC
NC
BW
B
BW
A
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1367C
(512K × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SSQ
NC
DQP
A
DQ
A
DQ
A
V
SSQ
V
DDQ
DQ
A
DQ
A
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SSQ
DQ
A
DQ
A
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
MODE
A
A
A
A
A
1
A
0
NC/72M
NC/36M
V
SS
V
DD
NC/18M
A
A
A
A
A
A
A
A
Document Number: 38-05542 Rev. *N
MODE
A
A
A
A
A
1
A
0
NC/72M
NC/36M
V
SS
V
DD
NC/18M
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Page 4 of 32
CY7C1366C
CY7C1367C
Pin Configurations
(continued)
Figure 2. 119-ball BGA (14 × 22 × 2.4 mm) pinout (2 Chip Enable with JTAG)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/288M
NC/144M
DQ
C
DQ
C
V
DDQ
DQ
C
DQ
C
V
DDQ
DQ
D
DQ
D
V
DDQ
DQ
D
DQ
D
NC
NC
V
DDQ
2
A
CE
2
A
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
A
NC/72M
TMS
CY7C1366C (256K × 36)
3
4
5
A
A
ADSP
A
A
V
SS
V
SS
V
SS
BW
C
V
SS
NC
V
SS
BW
D
V
SS
V
SS
V
SS
MODE
A
TDI
ADSC
V
DD
NC
CE
1
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
V
DD
A
TCK
A
A
V
SS
V
SS
V
SS
BW
B
V
SS
NC
V
SS
BW
A
V
SS
V
SS
V
SS
NC
A
TDO
6
A
A
A
DQP
B
DQ
B
DQ
B
DQ
B
DQ
B
V
DD
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
A
NC/36M
NC
7
V
DDQ
NC/576M
NC/1G
DQ
B
DQ
B
V
DDQ
DQ
B
DQ
B
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
NC
ZZ
V
DDQ
Document Number: 38-05542 Rev. *N
Page 5 of 32
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