PROTECTION PRODUCTS - RailClamp
®
Description
RailClamps are surge rated diode arrays designed to
protect high speed data interfaces. The SRDA series
has been specifically designed to protect sensitive
components which are connected to data and trans-
mission lines from overvoltage caused by electrostatic
discharge
(ESD),
electrical fast transients
(EFT),
and
lightning.
The unique design incorporates surge rated, low
capacitance steering diodes and a TVS diode in a
single package. During transient conditions, the
steering diodes direct the transient current to ground
via the internal low voltage TVS. The TVS diode clamps
the transient voltage to a safe level. The low capaci-
tance array configuration allows the user to protect up
to four high-speed data lines. The SRDA05-4 may be
used to protect lines operating up to 5 volts while the
SRDA12-4 may be used on lines operating up to 12
volts.
These devices are in a 8-pin SOIC package. They are
available with a SnPb or RoHS/WEEE compliant matte
tin lead finish. The high surge capability (Ipp=25A,
tp=8/20μs) means it can be used in high threat
environments in applications such as CO/CPE equip-
ment, telecommunication lines, and video lines.
RailClamp
®
Low Capacitance TVS Diode Array
Features
Transient protection for high-speed data lines to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning) 24A (8/20μs)
Array of surge rated diodes with internal TVS diode
Protects four I/O lines
Low capacitance (<15pF) for high-speed interfaces
Low operating and clamping voltages
Solid-state technology
SRDA05-4 and SRDA12-4
Mechanical Characteristics
JEDEC SOIC-8 package
Lead Finish: SnPb or Matte Sn
Molding compound flammability rating: UL 94V-0
Marking : Part number, date code, logo
Packaging : Tape and Reel per EIA 481
Applications
USB Power and Data Line Protection
T1/E1 secondary IC Side Protection
T3/E3 secondary IC Side Protection
HDSL, SDSL secondary IC Side Protection
Video Line Protection
Microcontroller Input Protection
Base stations
I
2
C Bus Protection
Circuit Diagram
Schematic and PIN Configuration
REF1
I/O 1
1
8
REF 2
I/O 1
I/O 2
I/O 3
I/O 4
REF 1
2
7
I/O 4
REF 1
REF2
3
6
I/O 3
I/O 2
4
5
REF 2
S0-8 (Top View)
Revision 8/21/07
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1
SRDA05-4 and SRDA12-4
PROTECTION PRODUCTS
Absolute Maximum Rating
R ating
Peak Pulse Power (t
p
= 8/20
μ
s)
Peak Forward Voltage (I
F
= 1A, t
p
=8/20
μ
s)
Lead Soldering Temp erature
Op erating Temp erature
Storage Temp erature
Symbol
P
p k
V
FP
T
L
T
J
T
STG
Value
500
1.5
260 (10 sec.)
-55 to +125
-55 to +150
Units
Watts
V
°C
°C
°C
Electrical Characteristics (T=25
o
C)
SR DA05-4
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamp ing Voltage
Clamp ing Voltage
Clamp ing Voltage
Peak Pulse Current
Junction Cap acitance
Symbol
V
RWM
V
BR
I
R
V
C
V
C
V
C
I
P P
C
j
I
t
= 1mA
V
RWM
= 5V, T=25°C
I
PP
= 1A, t
p
= 8/20
μ
s
I
PP
= 10A, t
p
= 8/20
μ
s
I
PP
= 25A, t
p
= 8/20
μ
s
t
p
= 8/20
μ
s
Between I/O p ins and
Ground
V
R
= 0V, f = 1MHz
Between I/O p ins
V
R
= 0V, f = 1MHz
8
6
10
9.8
12
20
25
15
Conditions
Minimum
Typical
Maximum
5
Units
V
V
μ
A
V
V
V
A
pF
4
pF
©
2007 Semtech Corp.
2
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SRDA05-4 and SRDA12-4
PROTECTION PRODUCTS
Electrical Characteristics
(continued)
SR DA12-4
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamp ing Voltage
Clamp ing Voltage
Clamp ing Voltage
Peak Pulse Current
Junction Cap acitance
Symbol
V
RWM
V
BR
I
R
V
C
V
C
V
C
I
P P
C
j
I
t
= 1mA
V
RWM
= 12V, T=25°C
I
PP
= 1A, t
p
= 8/20
μ
s
I
PP
= 10A, t
p
= 8/20
μ
s
I
PP
= 20A, t
p
= 8/20
μ
s
t
p
= 8/20
μ
s
Between I/O p ins and
Ground
V
R
= 0V, f = 1MHz
Between I/O p ins
V
R
= 0V, f = 1MHz
8
13.3
1
17
20
25
20
15
Conditions
Minimum
Typical
Maximum
12
Units
V
V
μ
A
V
V
V
A
pF
4
pF
©
2007 Semtech Corp.
3
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SRDA05-4 and SRDA12-4
PROTECTION PRODUCTS
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
10
Peak Pulse Power - P
pk
(kW)
Power Derating Curve
110
100
% of Rated Power or
PP
I
90
80
70
60
50
40
30
20
10
1
0.1
0.01
0.1
1
10
Pulse Duration - t
p
(µs)
100
1000
0
0
25
50
75
100
o
125
150
Ambient Temperature - T
A
( C)
Pulse Waveform
110
100
90
80
Percent of I
PP
70
60
50
40
30
20
10
0
0
5
10
15
T im e (µs)
20
25
30
td = I
PP
/2
e
-t
Clamping Voltage vs. Peak Pulse Current
W aveform
Parameters:
tr = 8µs
td = 20µs
22
20
Clamping Voltage - V
C
(V)
18
16
14
12
10
8
6
4
2
0
0
5
10
15
20
25
30
Peak Pulse Current - I
PP
(A)
Waveform
Parameters:
tr = 8µs
td = 20µs
SRDA3.3-4
SRDA05-4
SRDA12-4
Variation of Capacitance vs. Reverse Voltage
1.04
Forward Voltage vs. Forward Current
10
9
Forward Voltage - V
F
(V)
8
7
6
5
4
3
2
1
0
0
5
10
15
20
25
30
35
Waveform
Parameters:
tr = 8
μ
s
td = 20
μ
s
40
45
50
1.02
1
Cj (VR) / Cj (VR=0)
0.98
0.96
0.94
0.92
0.9
0.88
0
0.5
1
1.5
2
2.5
3
3.5
Reverse Voltage - VR (V)
Forward Current - I
F
(A)
©
2007 Semtech Corp.
4
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SRDA05-4 and SRDA12-4
PROTECTION PRODUCTS
Applications Information
Device Connection Options for Protection of Four
High-Speed Lines
The SRDA TVS is designed to protect four data lines
from transient overvoltages by clamping them to a
fixed reference. When the voltage on the protected
line exceeds the reference voltage (plus diode V
F
) the
steering diodes are forward biased, conducting the
transient current away from the sensitive circuitry.
Data lines are connected at pins 1, 4, 6 and 7. The
negative reference is connected at pins 5 and 8.
These pins should be connected directly to a ground
plane on the board for best results. The path length is
kept as short as possible to minimize parasitic induc-
tance.
The positive reference is connected at pins 2 and 3.
The options for connecting the positive reference are
as follows:
1. To protect data lines and the power line, connect
pins 2 & 3 directly to the positive supply rail (V
CC
).
In this configuration the data lines are referenced
to the supply voltage. The internal TVS diode
prevents over-voltage on the supply rail.
2. The SRDA can be isolated from the power supply by
adding a series resistor between pins 2 and 3 and
V
CC
. A value of 10kΩ is recommended. The
internal TVS and steering diodes remain biased,
providing the advantage of lower capacitance.
3. In applications where no positive supply reference
is available, or complete supply isolation is desired,
the internal TVS may be used as the reference. In
this case, pins 2 and 3 are not connected. The
steering diodes will begin to conduct when the
voltage on the protected line exceeds the working
voltage of the TVS (plus one diode drop).
ESD Protection With RailClamps
RailClamps are optimized for ESD protection using the
rail-to-rail topology. Along with good board layout,
these devices virtually eliminate the disadvantages of
using discrete components to implement this topology.
Consider the situation shown in Figure 1 where dis-
crete diodes or diode arrays are configured for rail-to-
rail protection on a high speed line. During positive
duration ESD events, the top diode will be forward
biased when the voltage on the protected line exceeds
the reference voltage plus the V drop of the diode.
F
For negative events, the bottom diode will be biased
©
2007 Semtech Corp.
5
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Data Line and Power Supply Protection Using Vcc as
reference
Data Line Protection with Bias and Power Supply
Isolation Resistor
Data Line Protection Using Internal TVS Diode as
Reference
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