Low Capacitance TVS Diode Array
For Multi-mode Transceiver Protection
PROTECTION PRODUCTS
Description
The LCDAxxC-8 has been specifically designed to
protect sensitive components which are connected to
data and transmission lines from over voltages caused
by electrostatic discharge
(ESD),
electrical fast tran-
sients
(EFT),
and
lightning.
The low capacitance array configuration of the
LCDAxxC-8 allows the user to protect eight high-speed
data or I/O lines. They may be used on systems
operating from 5 to 15 Volts. The high surge capability
(500W, tp=8/20µs) makes the LCDAxxC-8 suitable for
telecommunications systems operating in harsh tran-
sient environments. The low inductance construction
minimizes voltage overshoot during high current
surges.
The features of the LCDAxxC-8 are ideal for protecting
multi-protocol transceivers in WAN applications such as
Frame Relay systems, routers, and switches.
LCDA12C-8 and LCDA15C-8
Features
Transient protection for high-speed data lines to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning) 0.5kV, 12A (8/20µs)
Protects eight I/O lines
Low capacitance for high-speed interfaces
High surge capability
Low clamping voltage
Solid-state silicon avalanche technology
Mechanical Characteristics
JEDEC SO-16 package
Molding compound flammability rating: UL 94V-0
Marking : Part number, date code, logo
Packaging : Tape and Reel per EIA 481
Applications
Multi-Mode Transceiver Protection
WAN Equipment:
CSU/DSU
Multiplexers
Routers
ISP Equipment
Customer Premise Equipment
Protection for any of the following interfaces:
RS-232 (V.28)
RS-422 (V.11, X.21)
RS-449 (V.11/V.10)
Circuit Diagram
Schematic & PIN Configuration
Pin 1
Pin 16
SO-16 (Top View)
Revision 02/18/05
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LCDA12C-8 and LCDA15C-8
PROTECTION PRODUCTS
Absolute Maximum Rating
R ating
Peak Pulse Power (t
p
= 8/20µs)
Lead Soldering Temperature
Operating Temperature
Storage Temperature
Symbol
P
p k
T
L
T
J
T
STG
Value
500
260 (10 sec.)
-55 to +125
-55 to +150
Units
Watts
°C
°C
°C
Electrical Characteristics
LCDA12C-8
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamp ing Voltage
Clamp ing Voltage
Peak Pulse Current
Junction Cap acitance
Symbol
V
RWM
V
BR
I
R
V
C
V
C
I
P P
C
j
I
t
= 1mA
V
RWM
= 12V, T=25°C
I
PP
= 5A, t
p
= 8/20µs
I
PP
= 20A, t
p
= 8/20µs
t
p
= 8/20µs
Between I/O p ins and
Ground
V
R
= 0V, f = 1MHz
8
13.3
5
19
26.6
20
15
Conditions
Minimum
Typical
Maximum
12
Units
V
V
µA
V
V
A
pF
LCDA15C-8
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamp ing Voltage
Clamp ing Voltage
Peak Pulse Current
Junction Cap acitance
Symbol
V
RWM
V
BR
I
R
V
C
V
C
I
P P
C
j
I
t
= 1mA
V
RWM
= 15V, T=25°C
I
PP
= 1A, t
p
= 8/20µs
I
PP
= 15A, t
p
= 8/20µs
t
p
= 8/20µs
Between I/O p ins and
Ground
V
R
= 0V, f = 1MHz
2
Conditions
Minimum
Typical
Maximum
15
Units
V
V
16.7
5
24
33
15
8
15
µA
V
V
A
pF
2005 Semtech Corp.
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LCDA12C-8 and LCDA15C-8
PROTECTION PRODUCTS
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
10
Peak Pulse Power - P
pk
(kW)
Power Derating Curve
110
100
90
% of Rated Power or I
PP
80
70
60
50
40
30
20
10
1
0.1
0.01
0.1
1
10
Pulse Duration - t
p
(µs)
100
1000
0
0
25
50
75
100
125
o
150
175
Ambient Temperature - T
A
( C)
Pulse Waveform
110
100
90
80
Percent of I
PP
70
60
50
40
30
20
10
0
0
5
10
15
T im e (µs)
20
25
30
td = I
PP
/2
e
-t
W aveform
Parameters:
tr = 8µs
td = 20µs
Clamping Voltage vs. Peak Pulse Current
28
26
Clamping Voltage - V
C
(V)
24
22
20
18
16
14
12
10
0
5
10
15
20
25
Peak Pulse Current - I
PP
(A)
LCDA12C-8
Waveform
Parameters:
tr = 8µs
td = 20µs
LCDA15C-8
LCDA12C-8 Capacitance vs. Reverse Voltage
12
10
Capacitance - C
j
(pF)
8
6
4
2
0
0
2
4
6
8
10
Reverse Voltage - V
R
(V)
f = 1MHz
LCDA15C-8 Capacitance vs. Reverse Voltage
6
5
Capacitance - C
j
(pF)
4
3
2
1
f = 1MHz
0
12
0
2
4
6
8
10
12
14
Reverse Voltage - V
R
(V)
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LCDA12C-8 and LCDA15C-8
PROTECTION PRODUCTS
Applications Information
Device Connection Options for Protection of Eight
High-Speed Data Lines
The LCDAxxC-8 may be configured to protect up to
eight I/O lines operating between 5 and 15V. It may be
used to protect the most popular serial data interface
standard lines making it ideal for use in equipment
utilizing multi-mode transceivers. The LCDAxxC-8 is
symmetrical so the data lines may be connected at
pins 1-8 or 9-16. Pins 9-16 or 1-8 are connected to
ground as shown. For best results, these pins should
be connected directly to a ground plane on the board.
The path length should be kept as short as possible to
minimize parasitic inductance.
Multi-Mode Transceiver Protection
The LCDAxxC-8 may be used to protect multi-mode
transceiver I/O lines with external connections. The
LCDAxxC-8 adds a maximum loading capacitance of
15pF with a working voltage of 12V or 15V. This allows
the transceiver to safely operate in all modes without
clipping or degradation of the signal.
With proper design and layout, the transceiver port can
be protected to >15kV (HBM per IEC 61000-4-2).
Circuit Board Layout Recommendations for Suppres-
sion of ESD.
Good circuit board layout is critical for the suppression
of fast rise-time transients such as ESD. The following
guidelines are recommended:
Place the LCDAxxC-8 near the input terminals or
connectors to restrict transient coupling.
Minimize the path length between the LCDAxxC-8
and the protected line.
Minimize all conductive loops including power and
ground loops.
The ESD transient return path to ground should be
kept as short as possible.
Never run critical signals near board edges.
Use ground planes whenever possible.
Matte Tin Lead Finish
Matte tin has become the industry standard lead-free
replacement for SnPb lead finishes. A matte tin finish
is composed of 100% tin solder with large grains.
Since the solder volume on the leads is small com-
pared to the solder paste volume that is placed on the
land pattern of the PCB, the reflow profile will be
determined by the requirements of the solder paste.
Therefore, these devices are compatible with both
lead-free and SnPb assembly techniques. In addition,
unlike other lead-free compositions, matte tin does not
have any added alloys that can cause degradation of
the solder joint.
Device Connection
2005 Semtech Corp.
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LCDA12C-8 and LCDA15C-8
PROTECTION PRODUCTS
Outline Drawing - SO-16
h
A
N
2X E/2
E1 E
e
D
H
GAGE
PLANE
0.25
1
2
3
e/2
B
D
aaa C
A2 A
SEATING
PLANE
C
bxN
bbb
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MS-012, VARIATION AC.
h
DIMENSIONS
INCHES
MILLIMETERS
DIM
MIN NOM MAX MIN NOM MAX
A
A1
A2
b
c
D
E1
E
e
h
L
L1
N
01
aaa
bbb
ccc
-
.053
.069
-
.004
.010
-
.049
.065
-
.012
.020
-
.007
.010
.386 .390 .394
.150 .154 .157
.236 BSC
.050 BSC
-
.010
.020
.016 .028 .041
(.041)
16
-
0°
8°
.004
.010
.008
c
L
(L1)
DETAIL
01
ccc C
2X N/2 TIPS
A
SIDE VIEW
SEE DETAIL
A
-
1.35
1.75
-
0.10
0.25
-
1.25
1.65
-
0.31
0.51
-
0.17
0.25
9.80 9.90 10.00
3.80 3.90 4.00
6.00 BSC
1.27 BSC
-
0.25
0.50
0.40 0.72 1.04
(1.04)
16
-
0°
8°
0.10
0.25
0.20
A1
C A-B D
Land Pattern - SO-16
X
DIM
(C)
G
Z
C
G
P
X
Y
Z
DIMENSIONS
INCHES
MILLIMETERS
(.205)
.118
.050
.024
.087
.291
(5.20)
3.00
1.27
0.60
2.20
7.40
Y
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
REFERENCE IPC-SM-782A, RLP NO. 304A.
2.
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