(Preliminary)
38MHz to 320MHz Low Phase Noise VCXO
FEATURES
Typical 0.4ps RMS (12kHz to 20MHz) phase
jitter for.
Typical 25ps (typ.) peak to peak jitter.
Low phase noise output (@ 1MHz frequency
offset
o
-144dBc/Hz for 155.52MHz
o
-140dBc/Hz for 311.04MHz
19MHz to 40MHz crystal input.
38MHz to 320MHz output.
Available in LVPECL, LVDS, or LVCMOS
outputs.
No external varicap required.
Output Enable selector.
Wide pull range (±200ppm).
3.3V operation.
Available in 3x3 QFN or 16-pin TSSOP
packages.
PACKAGE PIN ASSIGNMENT
VDDANA
XIN
XOUT
SEL2^
OE_CTRL
VCON
GNDANA
LP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL0^
SEL1^
GNDBUF
QBAR
VDDBUF
Q
GNDBUF
LM
VDDANA
SEL0^
10
XOUT
SEL2^
OE_CTRL
VCON
12
13
14
15
16
1
11
SEL1^
9
XIN
8
7
6
GNDBUF
QBAR
VDDBUF
Q
DESCRIPTION
The PL580-3X is a monolithic low jitter and low phase
noise VCXO, capable of 0.4ps RMS phase jitter and
LVCMOS, LVDS, or LVPECL outputs, covering a wide
frequency output range up to 320MHz. It allows the
control of the output frequency with an input voltage
(VCON), using a low cost crystal.
The frequency selector pads of the PL580-3X enable
output frequencies of (2, 4, 8, or 16) * F
XIN
. The PL580-
3X is designed to address the demanding requirements
of high performance applications such as SONET, GPS,
Video, etc.
2
3
4
5
GNDANA
16-pin TSSOP
3x3 QFN
Note1: QBAR is used for single ended LVCMOS output
.
Note2: ^ Denotes internal pull up resistor.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 8/19/09 Page 1
GNDBUF
LP
LM
(Preliminary)
38MHz to 320MHz Low Phase Noise VCXO
OUTPUT ENABLE LOGIC LEVELS
Part #
PL580-38 (LVPECL)
PL580-35 (LVPECL)
PL580-37 (LVCMOS)
PL580-39 (LVDS)
OE
0 (Default)
1
0
1 (Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
Note:
Connect to VDD to set to "1", connect to GND to set to "0".
In case of "0 (Default)" an internal pull-down resistor will set to "0" when pin is left open.
In case of "1 (Default)" an internal pull-up resistor will set to "1" when pin is left open.
PIN DESCRIPTIONS
Name
VDDANA
XIN
XOUT
SEL2
OE_CTRL
VCON
GNDANA
LP
LM
GNDBUF
Q
VDDBUF
QBAR
GNDBUF
SEL1
SEL0
TSSOP
Pin number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
3x3mm QFN
Pin number
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
Type
P
I
O
I
I
I
P
-
-
P
O
P
O
P
I
I
Description
V
DD
for analog Circuitry.
Crystal input pin. (See Crystal Specifications on page 4).
Crystal output pin. (See Crystal Specifications on page 4).
Output frequency Selector pin.
Output enable control pin. (See OUTPUT ENABLE LOGIC
LEVELS above).
Voltage control input.
Ground for analog circuitry.
Tuning inductor connection. The inductor is recommended
to be a high Q small size 0402 or 0603 SMD component,
and must be placed between LP and adjacent LM pin.
Place inductor as close to the IC as possible to minimize
parasitic effects and to maintain inductor Q.
GND connection for output buffer circuitry.
LVPECL or LVDS output.
V
DD
connection for output buffer circuitry. VDDBUF should be
separately decoupled from other VDDs whenever possible.
Complementary LVPECL, LVDS, Or single ended LVCMOS
output.
GND connection for output buffer circuitry.
Output frequency Selector pin.
Output frequency Selector pin.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 8/19/09 Page 2
(Preliminary)
38MHz to 320MHz Low Phase Noise VCXO
FREQUENCY SELECTION TABLE
SEL2
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
Selected Multiplier/Output Frequency
VCO Max*
VCO Min*
Reserved
Reserved
F
XTAL
x 2
F
XTAL
x 8
F
XTAL
x 16
F
XTAL
x 4
All SEL pads have internal pull-ups (default value is ‘1’). Bond to GND to set to 0.
* Special Test Modes to help selecting the inductor value for the target output frequency.
PERFORMANCE TUNING & INDUCTOR VALUE SELECTION
Please refer to PhaseLink’s ‘PhasorV Tuning Assistance’ software to automatically calculate the optimum inductor
values for your application. In addition, the chart below could be used as a reference for quick inductor value
selection. Please note that the inductor values mentioned in the table below, or when using ‘PhasorV Tuning
Assistance’ are derived based on the parasitic values of PhaseLink’s evaluation board. For performance
enhancement of your custom board design, please follow the following instruction:
Use the special test modes “VCO Max” and “VCO Min” to determine the optimum inductor value. “VCO Max”
represents the high end of the VCO range and “VCO Min” represents the low end of the VCO range. The output
frequency in the “VCO Max” and “VCO Min” test modes is VCO/16. This means that the output frequencies are
around the crystal frequency that will be used. The optimum inductor value is where the target crystal frequency
is closest to the middle between the “VCO Max” and “VCO Min” output frequencies. In this case the VCO will lock
in the middle of its tuning range with maximum margin on either side.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 8/19/09 Page 3
(Preliminary)
38MHz to 320MHz Low Phase Noise VCXO
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
2
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
-0.5
-0.5
-65
-40
MIN.
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
UNITS
V
V
V
C
C
C
C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.*
Note:
Operating Temperature is guaranteed by design for all parts
(COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
Crystal Resonator
Frequency
Crystal Loading Rating
Crystal Pullability
Recommended ESR
SYMBOL
F
XTAL
CONDITIONS
Parallel Fundamental Mode
at VCON = 0V
C
L (XTAL)
at VCON = 1.65V
at VCON = 3.3V
C
0
/C
1 (XTAL)
AT cut
R
E
AT cut
MIN.
19
17.7
9.5
5.4
250
30
-
Ω
pF
TYP.
MAX.
40
UNITS
MHz
Note:
Crystal Loading rating: The listed numbers are for the IC only. Specify the crystal for the value at VCON = 1.65V and add the PCB & package
parasitic. A round number (i.e. 12pF) can be achieved by adding external capacitors. Try to add the same value to XIN and XOUT, and please note,
that frequency pulling and oscillator gain may decrease.
3. General Electrical Specifications
PARAMETERS
Supply Current, Dynamic
(with Loaded Outputs)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
Note:
LVCMOS output is not advised above 200MHz with 15pF load; and 320MHz with 10pF load.
SYMBOL
I
DD
V
DD
CONDITIONS
LVPECL/ 38MHz<F
OUT
<100MHz
LVDS/
LVCMOS 100MHz<F
OUT
<320MHz
MIN.
TYP.
MAX.
65/45/30
80/60/40
UNITS
mA
V
%
mA
2.97
@ 50% V
DD
(LVCMOS)
@ 1.25V (LVDS)
@ V
DD
– 1.3V (LVPECL)
45
50
50
3.63
55
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 8/19/09 Page 4
(Preliminary)
38MHz to 320MHz Low Phase Noise VCXO
4. Voltage Control Crystal Oscillator
PARAMETERS
SYMBOL
CONDITIONS
From power valid
F
XTAL
= 19 to 40MHz;
XTAL C
0
/C
1
< 250
0V
VCON
3.3V
VCON=1.65V,
1.65V
MIN.
TYP.
MAX.
10
500
200
150
10
60
0V
VCON
3.3V, -3dB
25
80
UNITS
ms
ppm
ppm
ppm/V
%
kΩ
kHz
VCXO Stabilization Time * T
VCXOSTB
VCXO Tuning Range
CLK Output Pullability
VCXO Tuning
Characteristic
Pull Range Linearity
VCON Input Impedance
VCON Modulation BW
Note:
Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
5. Jitter Specifications
PARAMETERS
Integrated Jitter RMS
CONDITIONS
With capacitive decoupling
between V
DD
and GND.
Integrated 12kHz to 20MHz
With capacitive decoupling
between V
DD
and GND.
Over 10,000 cycles.
FREQUENCY
155.52MHz
311.04MHz
77.76MHz
155.52MHz
311.04MHz
77.76MHz
155.52MHz
311.04MHz
MIN.
TYP.
0.4
0.4
2.5
3
4
18
20
25
MAX.
0.5
0.5
4
5
7
30
30
35
ps
ps
UNITS
ps
Period Jitter RMS
With capacitive decoupling
Period Jitter Peak-to-Peak between V
DD
and GND.
Over 10,000 cycles.
6. Phase Noise Specifications
PARAMETERS
Phase Noise
relative to
carrier (typical)
FREQ.
77.76MHz
155.52MHz
311.04MHz
@10Hz
-66
-62
-59
@100Hz
-96
-92
-86
@1kHz
-124
-120
-116
@10kHz @100kHz
-134
-132
-129
-132
-128
-124
@1M
-145
-144
-140
@10M
-149
-150
-148
UNITS
dBc/Hz
Note: Phase Noise measured at VCON = 0V.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 8/19/09 Page 5
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