32.768 kHz ±5 ppm all-inclusive frequency stability
In-system auto-calibration:
- Compensates for board-level stress-induced frequency errors
- Improves all-inclusive frequency stability
World’s smallest TCXO Footprint: 1.2 mm
- 1.5 x 0.8 mm CSP
- No external bypass cap required
Drives multiple loads and eliminates multiples XTALs
Low integrated phase jitter (IPJ) suitable for multiplying up for
portable audio: 2.5ns
RMS
Ultra-low power: 4.5 µA
Supply voltage: 1.8V ±10%
Operating temperature ranges: -20°C to +70°C, -40°C to +85°C
Pb-free, RoHS and REACH compliant
2
Smart watches, health and wellness monitors
Ultra-accurate RTC reference clock
Smart utility meters, E-meters
Internet of Things (IoT)
Electrical Characteristics
Conditions: Min/Max limits are over temperature, Vdd = 1.8V ±10%, unless otherwise stated. Typicals are at 25°C and Vdd = 1.8V.
Parameter
Symbol
Min.
Typ.
Max.
Unit
Condition
Frequency and Stability
Output Frequency
Total Frequency Stability after
Overmold
[1]
Total Frequency Stability without
Overmold or Calibration
[1]
Allan Deviation
First Year Frequency Aging
AD
F_aging
Fout
F_stab
-5
-25
-5
1e-8
±1
32.768
5
25
5
4e-8
kHz
ppm
ppm
ppm
-
ppm
All inclusive,
after
overmold,
post in-system calibration.
All inclusive,
after
overmold,
before
in-system calibration.
All inclusive, under influence of up to 5°C/sec temp
gradient and board-level underfill.
1 second averaging time.
T
A
= 25°C, Vdd = 1.8V, with overmold.
Integration bandwidth = 100 Hz to 16.384 kHz. Inclusive of
50 mV peak-to-peak sinusoidal noise on Vdd. Noise frequency
100 Hz to 20 MHz.
10,000 samples, per JEDEC standard 65B
Jitter and Frequency Response Performance
Integrated Phase Jitter
RMS Period Jitter
Peak-to-Peak Period Jitter
Dynamic Temperature
Frequency Response
IPJ
PJ
RMS
PJ
p-p
-0.5
1.8
2.5
20
2.5
4
35
+0.5
ns
RMS
ns
RMS
ns
p-p
ppm/sec
Under temp ramp up to 1.5°C/sec
Supply Voltage and Current Consumption
Operating Supply Voltage
Supply Current
Start-up Time at Power-up
Vdd
Idd
t_start
1.62
1.8
4.5
1.98
5.3
300
V
µA
ms
No Load.
Measured when supply reaches 90% of final Vdd to the first
output pulse.
“C” ordering code.
“I” ordering code.
Operating Temperature Range
Operating Temperature Range
Op_Temp
-20
-40
70
85
LVCMOS Output
Output Rise/Fall Time
Output Clock Duty Cycle
Output Voltage High
Output Voltage Low
tr, tf
DC
VOH
VOL
45
90%
10%
9
20
55
ns
%
Vdd
Vdd
I
OH
= -1 µA
I
OL
= 1 µA
10-90% (Vdd), 15 pF Load.
°C
°C
Note:
1. Contact Factory for specific overmold conditions. Relative to 32.768 kHz, includes initial tolerance, over temp, Vdd, load, hysteresis, board-level underfill, and, 3x
reflow. Tested with Agilent 53132A frequency counter. Measured with 100ms gate time for accurate frequency measurement.
SiTime Corporation
Rev 0.8
990 Almanor Avenue, Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised March 10, 2016
SiT1568
1.2mm
2
Micropower, 5 ppm, 32.768 kHz TCXO with
In-System Auto-Calibration
The Smart Timing Choice
Pin Configuration
CSP
Pin
1
2
3
4
Symbol
Auto-Cal or
NC
CLK Out
Vdd
GND
I/O
Functionality
Used for communicating calibration information to the chip for improving stability in the
presence of board level induced stresses. Leave pin floating (NC) when not using the
calibration function.
Oscillator clock output.
1.8V
±10%
power supply. For most applications, the internal bypass filtering is
acceptable. A PSNR plot is shown in the Typ Ops section. If power-supply bypassing is
required, a 10-100 nF low ESR, ceramic capacitor is acceptable.
Connect to ground.
Control Input
OUT
Power Supply
Power Supply
Ground
CSP Package (Top View)
CAL/NC
1
4
GND
CLK Out
2
3
Vdd
Absolute Maximum Ratings
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of
the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameters
Continuous Power Supply Voltage Range (Vdd)
Continuous Maximum Operating Temperature Range
Human Body Model (HBM) ESD Protection
Charge-Device Model (CDM) ESD Protection
Machine Model (MM) ESD Protection
Latch-up Tolerance
Mechanical Shock Resistance
Mechanical Vibration Resistance
1508 CSP Junction Temperature
Storage Temperature
Mil 883, Method 2002
Mil 883, Method 2007
JESD22-A114
JESD22-C101
T
A
= 25°C
JESD78 Compliant
20,000
70
150
-65 to 150
g
g
°C
°C
Test Conditions
Value
-0.5 to 4.0
105
2000
750
200
Unit
V
°C
V
V
V
System Block Diagram
MEMS Resonator
GND
Control
Regulators
Vdd
Temp
Control
Temp-to-Digital
Prog
Prog
NVM
Cal/NC
Sustaining
Amp
Ultra-low
Power
Frac-n
PLL
Divider
Driver
CLK Out
Figure 1. SiT1568 Block Diagram
Rev. 0.8
Page 2 of 12
www.sitime.com
SiT1568
1.2mm
2
Micropower, 5 ppm, 32.768 kHz TCXO with
In-System Auto-Calibration
The Smart Timing Choice
Description
SiT1568 is an ultra-small and ultra-low power 32.768 kHz
TCXO optimized for battery-powered applications. SiTime’s
silicon MEMS technology enables the first 32 kHz TCXO in the
world’s smallest footprint and chip-scale packaging (CSP).
Typical supply current is 4.5 µA under no load condition.
SiTime's MEMS oscillator consists of a MEMS resonator and
a programmable analog circuit. SiT1568 MEMS resonator is
built with SiTime’s unique MEMS First™ process. A key
manufacturing step is EpiSeal™ during which the MEMS
resonator is annealed with temperatures over 1000°C.
EpiSeal creates an extremely strong, clean, vacuum chamber
that encapsulates the MEMS resonator and ensures the best
performance and reliability. During EpiSeal, a poly silicon cap
is grown on top of the resonator cavity, which eliminates the
need for additional cap wafers or other exotic packaging. As a
result, SiTime’s MEMS resonator die can be used like any
other semiconductor die. One unique result of SiTime’s MEMS
First and EpiSeal manufacturing processes is the capability to
integrate SiTime’s MEMS die with a SOC, ASIC, micropro-
cessor or analog die within a package to eliminate external
timing components and provide a highly integrated, smaller,
cheaper solution to the customer.
In-System Auto Calibration
SiT1568 provides a unique, in-system calibration feature that
compensates for assembly-related frequency offsets for
improved overall frequency stability. The on-chip auto-
calibration function is performed one-time during the
customer's production system manufacturing process. In
order to initiate the one-time auto calibration process, refer to
the pin 1 auto-calibration description.
After assembly, follow the calibration steps as shown in the
flow chart (Figure 2). Connect pin 1 to a 10 MHz reference
(GPS disciplined or equivalent) and monitor the SiT1568 CLK
Out for status and error flags. A summary of these flags is
shown in Table 1. SiT1568 will compare its 32.768 kHz (plus
the assembly-related error) frequency to the accurate
10 MHz reference, calibrate (remove) the error and store the
calibration in its internal non-volatile memory. The result is a
calibrated 32.768 kHz output frequency with an overall stability
(accuracy) of ±5 ppm. The entire auto-calibration process
typically takes about 2 seconds.
Auto calibration is intended to be performed one time to
remove the board-related offset errors. The auto-calibration
procedure can be repeated if process fails during the initial
steps (see Table 1). The maximum number of retries is deter-
mined by the customer.
TCXO Frequency Stability
SiT1568 is factory calibrated (trimmed) over multiple temper-
ature points to guarantee extremely tight stability over temper-
ature. Unlike quartz crystals that have a classic tuning fork
parabola temperature curve with a 25°C turnover point with a
0.04 ppm/C
2
temperature coefficient, the SiT1568 temper-
ature coefficient is calibrated and corrected over temperature
with an active temperature correction circuit. The result is a
32 kHz TCXO with extremely tight frequency variation over the
-40°C to +85°C temperature range.
When measuring the output frequency of SiT1568 with a
frequency counter, it is important to make sure the counter's
gate time is >100 ms. Shorter gate times may lead to
inaccurate measurements.
Dynamic Temperature Frequency Response
Dynamic Temperature Frequency Response is the rate of
frequency change during temperature ramps. This is an
important performance metric when the oscillator is mounted
near a high power component (e.g. SoC or power
management) that may rapidly change the temperature of
surrounding components.
For moderate temperature ramp rates (< 2°C/sec), the
dynamic response is primarily determined by the steady-
state frequency vs. temperature of the device. The best
dynamic response is obtained from parts which have been
trimmed to be flat in frequency over temperature.
For high temperature ramp rates (>5°C/sec), the latency in
the temperature compensation loop contributes a larger
frequency error, which is dependent on the temperature
compensation update rate. This part achieves excellent
performance at 3Hz update rate. This device family supports
faster update rates for further reducing dynamic frequency
error at the expense of slightly increased current
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