MITSUBISHI LSIs
MH4M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
PIN CONFIGURATION (TOP VIEW)
DESCRIPTION
The MH4M365CXJ/CNXJ is 4194304-word x 36-bits dynamic
RAM. This consists of eight industry standard 4M x 4 dynamic
RAMs in SOJ and four industry 4M x 1 dyanmic RAMs in SOJ.
The mounting of SOJ on a single in-line package provides any
application where high densities and large quantities of memory
are required. This is a socket-type memory module,suitable for
easy interchange or addition of modules.
[Double side]
1.Vss
2.DQ0
3.DQ16
4.DQ1
5.DQ17
6.DQ2
37.MP1
38.MP3
39.Vss
40.CAS0
41.CAS2
42.CAS3
43.CAS1
44.RAS0
45.NC
46.NC
47.W
48.NC
49.DQ8
50.DQ24
51.DQ9
52.DQ25
53.DQ10
54.DQ26
55.DQ11
FEATURES
Type name
MH4M365CXJ/CNXJ-5
MH4M365CXJ/CNXJ-6
MH4M365CXJ/CNXJ-7
RAS
CAS
access access
time
time
(max.ns) (max.ns)
Address Cycle
Power
access
dissipa-
time
time
tion
(max.ns) (min.ns) (typ.mW)
7.DQ18
8.DQ3
11.NC
10.Vcc
11.NC
12.A0
13.A1
14.A2
15.A3
50
60
70
13
15
20
25
30
35
90
110
130
7240
5920
5200
72pin single in-line package
Single 5.0V ± 10% supply
Low stand-by power dissipation
44mW (Max)
Low operating power dissipation
MH4M365CXJ/CNXJ- 5
MH4M365CXJ/CNXJ- 6
MH4M365CXJ/CNXJ- 7
16.A4
17.A5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CMOS lnput level
9.15W (Max)
7.48W (Max)
6.51W (Max)
18.A6
19.A10
20.DQ4
21.DQ20
22.DQ5
Hyper-page mode , RAS-only refresh , CAS before RAS
refresh, Hidden refresh capabilities
All inputs and output directly TTL compatible
2048 refresh cycles every 32ms (A
0
~ A
10
)
MH4M365CXJ
MH4M365CNXJ
Gold plating
Nickel+solder plating
23.DQ21
24.DQ6
25.DQ22
26.DQ7
27.DQ23
28.A7
29.NC
APPLICATION
Main memory unit for computers, Microcomputer memory,
Refresh memory for CRT
30.Vcc
31.A8
32.A9
33.NC
34.RAS2
35.MP2
36.MP0
56.DQ27 37
38
57.DQ12 39
40
41
58.DQ28 42
43
59.Vcc
44
45
60.DQ29 46
47
61.DQ13 48
49
62.DQ30 50
51
63.DQ14 52
53
64.DQ31 54
55
56
65.DQ15 57
58
66.NC
59
60
67.PD1 61
62
68.PD2 63
64
69.PD3 65
66
70.PD4 67
68
69
71.NC
70
71
72.Vss
72
Outline 72N9D-C
PD1
PD2
PD3
PD4
-5
Vss
NC
Vss
Vss
-6
Vss
NC
NC
NC
-7
Vss
NC
Vss
NC
NC: NO CONNECTION
MIT-DS-0086-1.1
MITSUBISHI
ELECTRIC
( 1 / 15 )
Nov.8.96
MITSUBISHI LSIs
MH4M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
FUNCTION
in addition to normal read, write, a number of other
functions, e.g., hyper page mode, RAS only refresh,
The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Inputs
Operation
RAS
Read
Early write
RAS-only refresh
Hidden refresh
CAS before RAS refresh
Standby
ACT
ACT
ACT
ACT
ACT
NAC
CAS
ACT
ACT
NAC
ACT
ACT
DNC
W
NAC
ACT
DNC
NAC
DNC
DNC
Row
address
APD
APD
APD
APD
DNC
DNC
Column
address
APD
APD
DNC
DNC
DNC
DNC
Input/Output
Input
OPN
VLD
DNC
OPN
DNC
DNC
Output
VLD
OPN
OPN
VLD
OPN
OPN
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid,APD : applied, OPN : open
BLOCK DIAGRAM
DQ1 DQ3
DQ5 DQ7 DQ9 DQ11 DQ13 DQ15
DQ0 DQ2
DQ4 DQ6 DQ8 DQ10 DQ12 DQ14
MP0
MP1
MP2
MP3
DQ17 DQ19 DQ21 DQ23 DQ25 DQ27 DQ29 DQ31
DQ16 DQ18 DQ20 DQ22 DQ24 DQ26 DQ28 DQ30
2 4 6 8
20 22 24 26 49 51 53 55 57 61 63 65
36
37
35
38
3 5 7 9
21 23 25 27 50 52 54 56 58 60 62 64
M5M
417405CJ
M5M
417405CJ
M5M
417405CJ
M5M
417405CJ
M5M
44105CJ
M5M
44105CJ
M5M
44105CJ
M5M
44105CJ
M5M
417405CJ
M5M
417405CJ
M5M
417405CJ
M5M
417405CJ
40 44
CAS0
RAS0
43
CAS1
12 13 14 15 16 17 18 28 31 32 19
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
41
CAS2
42 34 47
CAS3
W
RAS2
MIT-DS-0086-1.1
MITSUBISHI
ELECTRIC
( 2 / 15 )
Nov.8.96
MITSUBISHI LSIs
MH4M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
VI
V0
I0
Pd
Topr
Tstg
Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature
Ta=25 C
With respect to Vss
Parameter
Conditions
Ratings
-1 ~ 7
-1 ~ 7
-1 ~ 7
50
12
0 ~ 70
-40 ~ 125
Unit
V
V
V
mA
W
C
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Vcc
Vss
V
IH
V
IL
Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage, all inputs
Parameter
(Ta=0 ~ 70 °C, unless otherwise noted)
(Note 1)
Limits
Unit
V
V
V
V
Min
4.5
0
2.4
-1
Nom
5.0
0
Max
5.5
0
5.5
0.8
Note 1 : All voltage values are with respect to Vss
ELECTRICAL CHARACTERISTICS
Symbol
V
OH
V
OL
I
OZ
I
I
Parameter
High-level output voltage
Low-level output voltage
Off-state output current
Input current
Average supply current
from Vcc operating
(Note 3,4,5)
I
CC2
(Ta=0 ~ 70°C, Vcc=5.0V ± 10%, Vss=0V, unless otherwise noted)
(Note 2)
Test conditions
I
OH
=-5.0mA
I
OL
=4.2mA
Q floating 0V
≤
V
OUT
≤
5.5V
0V
≤
V
IN
≤
6 V, Other inputs pins=0V
Limits
Min
2.4
0
-20
-120
Typ
Max
Vcc
0.4
20
120
1660
1360
1180
RAS= CAS =V
IH,
output open
RAS= CAS
≥
Vcc - 0.2 V
RAS cycling, CAS= V
IH
t
RC
=min.
output open
24
8
1660
1360
1180
1620
1320
1060
1580
1300
1140
mA
mA
mA
mA
mA
Unit
V
V
µA
µA
MH4M365C
MH4M365C
MH4M365C
-5
-6
-7
I
CC1 (AV)
RAS, CAS cycling
t
RC
=t
WC
=min.
output open
Supply current from Vcc , stand-by (Note 6)
Average supply current
from Vcc refreshing
(Note 3,5)
Average supply current
from Vcc
Hyper-Page-Mode
(Note 3,4,5)
Average supply current
from Vcc
CAS before RAS refresh
mode
(Note 3)
MH4M365C
MH4M365C
MH4M365C
MH4M365C
MH4M365C
MH4M365C
MH4M365C
MH4M365C
MH4M365C
-5
-6
-7
-5
-6
-7
-5
-6
-7
I
CC3 (AV)
I
CC4(AV)
RAS=V
IL,
CAS cycling
t
PC
=min.
output open
I
CC6(AV)
CAS before RAS refresh cycling
t
RC
=min.
output open
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc3 (AV) and Icc4 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Column Address can be changed once or less while RAS=V
IL
and CAS=V
IH
.
MIT-DS-0086-1.1
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ELECTRIC
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Nov.8.96
MITSUBISHI LSIs
MH4M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
CAPACITANCE
(Ta=0 ~ 70 °C, Vcc=5.0V ± 10%, Vss=0V, unless
Symbol
C
I (A)
C
I (W)
C
I (RAS)
C
I (CAS)
C
I / O
Parameter
Input capacitance,address inputs
Input capacitance, write control input
Input capacitance, RAS input
Input capacitance, CAS input
Input/Output capacitance, data ports
V
I
=Vss
otherwise noted)
Test conditions
Limits
Min
Typ
Max
78
84
42
42
22
Unit
pF
pF
pF
pF
pF
f=1MH
Z
Vi=25mVrms
SWITCHING CHARACTERISTICS
Symbol
(Ta=0 ~ 70 °C, Vcc = 5V ± 10%, Vss=0V, unless otherwise noted , see notes 6,14,15)
Limits
Parameter
Access time from CAS
Access time from RAS
Column address access time
Access time from CAS precharge
Output hold time from CAS
(Note 13)
Output hold time from RAS
Output low impedance time from CAS low (Note 7)
(Note 12)
Output disable time after WE high
Output disable time after CAS high
Output disable time after RAS high
(Note 12,13)
(Note 12,13)
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
MH4M365C -5
Min
Max
13
50
25
30
5
5
5
13
13
13
MH4M365C -6
Min
Max
15
60
30
35
5
5
5
15
15
15
MH4M365C -7
Min
Max
20
70
35
40
5
5
5
20
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CAC
t
RAC
t
AA
t
CPA
t
OHC
t
OHR
t
CLZ
t
WEZ
t
OFF
t
REZ
Note 6: An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing a RAS clock such as RAS-Only refresh).
Note the RAS may be cycled during the initial pause . And any 8 RAS or RAS/CAS cycles are required after prolonged periods
(greater than 32 ms) of RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-5mA) / VOL=0.4V(IOL=-4.2mA) load 100pF.
The reference levels for measuring of output signal are 2.0V(VOH) and 0.8V(VOL).
8: Assumes that t
RCD
≥
t
RCD(max)
and t
ASC
≥
t
ASC(max)
and t
CP
≥t
CP(max).
9: Assumes that t
RCD
≤
t
RCD(max)
and t
RAD
≤
t
RAD(max).
If t
RCD
or t
RAD
is greater than the maximum recommended value shown in this table,
t
RAC
will increase by amount that t
RCD
exceeds the value shown.
10: Assumes that t
RAD
≥
t
RAD(max)
and t
ASC
≤
t
ASC(max).
11: Assumes that t
CP
≤
t
CP(max)
and t
ASC
≥
t
ASC(max).
12: t
WEZ(max) ,
t
OFF(max)
and t
REZ(max)
defines the time at which the output achieves the high impedance state (
and is not reference to V
OH(min)
or V
OL(max).
13: Output is disabled after both RAS and CAS go to high.
I
OUT
≤
I ± 10 µA I)
MIT-DS-0086-1.1
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ELECTRIC
( 4 / 15 )
Nov.8.96
MITSUBISHI LSIs
MH4M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Refresh, and Hyper-Page Mode Cycles)
(Ta=0 ~ 70°C, Vcc = 5V ± 10%, Vss=0V, unless otherwise noted See notes 14,15)
Limits
MH4M365C -6
Min
40
37
20
5
0
10
25
10
15
0
0
10
10
50
1
50
13
30
45
Max
32
50
20
5
0
13
15
0
0
10
10
1
50
13
35
50
Symbol
Parameter
Refresh cycle time
RAS high pulse width
Delay time, RAS low to CAS low
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
MH4M365C -5
Min
Max
32
30
(Note16)
18
5
0
8
(Note17)
(Note18)
13
0
0
8
8
(Note19)
1
MH4M365C -7
Min
Max
32
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
REF
t
RP
t
RCD
t
CRP
t
RPC
t
CPN
t
RAD
t
ASR
t
ASC
t
RAH
t
CAH
t
T
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low
Column address hold time after CAS low
Transition time
Note 14: The timing requirements are assumed t
T
=3ns.
15: V
IH(min)
and V
IL(max)
are reference levels for measuring timing of input signals.
16: t
RCD(max)
is specified as a reference point only. If t
RCD
is less than t
RCD(max),
access time is t
RAC.
If t
RCD
is greater than t
RCD(max),
access
time is controlled exclusively by t
CAC
or t
AA.
17: t
RAD(max)
is specified as a reference point only. If t
RAD
≤
t
RAD(max)
and t
ASC
≤
t
ASC(max),
access time is controlled exclusively by t
AA.
18: t
ASC(max)
is specified as a reference point only. If t
RCD
≥
t
RCD(max)
and t
ASC
≥
t
ASC(max),
access time is controlled exclusively by t
CAC.
19: t
T
is measured between V
IH(min)
and V
IL(max).
Read and Refresh Cycles
Symbol
Parameter
Read cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read Setup time before CAS low
Read hold time after CAS high
Read hold time after RAS high
Column address to RAS hold time
Column address to CAS hold time
(Note 20)
(Note 20)
MH4M365C
Min
90
50
8
40
13
0
0
0
25
13
10000
10000
-5
Limits
MH4M365C
Min
110
60
10
48
15
0
0
0
30
18
10000
10000
-6
MH4M365C
Min
130
70
13
55
20
0
0
0
35
23
10000
10000
-7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max
Max
Max
t
RC
t
RAS
t
CAS
t
CSH
t
RSH
t
RCS
t
RCH
t
RRH
t
RAL
t
CAL
Note 20: Either t
RCH
or t
RRH
must be satisfied for a read cycle.
MIT-DS-0086-1.1
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ELECTRIC
( 5 / 15 )
Nov.8.96
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