– Modem control functions (CTS, RTS, DSR, DTR, RI, DCD)
– 16-byte transmit and receive buffers
– Programmable baud rate generator derived from the system
clock
– Fully programmable serial characteristics:
– 5, 6, 7, or 8 bit characters
– Even, odd or no parity bit generation and detection
– 1, 1-1/2 or 2 stop bit generation
– Line break generation and detection
– False start bit detection
– Internal loopback mode
◆
2
I C-Bus
– Supports standard 100 Kbps mode as well as 400 Kbps fast
mode
– Supports 7-bit and 10-bit addressing
– Supports four modes: master transmitter, master receiver,
slave transmitter, slave receiver
◆
Additional General Purpose Peripherals
– Two 16550-compatible serial ports
– Interrupt controller
– System integrity functions
– General purpose I/O controller
– Serial peripheral interface (SPI)
◆
On-chip Memory
– 4KB of high speed SRAM organized as 1K x 32 bits
– Supports burst and non-burst byte, halfword, triple-byte, and
word CPU, PCI, and DMA accesses
◆
Debug Support
– Rev. 2.6 compliant EJTAG Interface
◆
memory with minimal CPU intervention using a highly sophisticated
direct memory access (DMA) engine. All data transfers through the
RC32438 are achieved by writing data from an on-chip I/O peripheral to
main memory and then out to another I/O module.
CPU Execution Core
The 32-bit CPU core is 100% compatible with the MIPS32 instruction
set architecture (ISA).
Specifically, this device features the 4Kc CPU core developed by
MIPS Technologies Inc. (www.mips.com). This core issues a single
instruction per cycle, includes a five stage pipeline, and is optimized for
applications that require integer arithmetic. The CPU core includes 16
KB instruction and 16 KB data caches. Both caches are 4-way set asso-
ciative and can be locked on a per line basis, which allows the
programmer control over this precious on-chip memory resource. The
core also features a memory management unit (MMU). The CPU core
also incorporates an enhanced joint test access group (EJTAG) inter-
face that is used to interface to in-circuit emulator tools, providing
access to internal registers and enabling the part to be controlled exter-
nally, simplifying the system debug process. The use of this core allows
IDT's customers to leverage the broad range of software and develop-
ment tools available for the MIPS architecture, including operating
systems, compilers, and in-circuit emulators.
Double Data Rate Memory Controller
The RC32438 incorporates a high performance double data rate
(DDR) memory controller which supports both x16 and x32 memory
configurations up to 2GB. This module provides all of the signals
required to interface to both memory modules and discrete devices,
including two chip selects, differential clocking outputs and data strobes.
Memory and I/O Controller
The RC32438 uses a dedicated local memory/IO controller including
a de-multiplexed 16-bit data and 26-bit address bus. It includes all of the
signals required to interface directly to as many as six Intel or Motorola-
style external peripherals, and the interface can be configured to
support both 8-bit and 16-bit peripherals.
DMA Controller
The DMA controller consists of 10 independent DMA channels, all of
which operate in exactly the same manner. The DMA controller off-loads
the CPU core from moving data among the on-chip interfaces, external
peripherals, and memory. The controller supports scatter/gather DMA
with no alignment restrictions, appropriate for communications and
graphics systems.
PCI Interface
The PCI interface on the RC32438 is compatible with version 2.2 of
the PCI specification. An on-chip arbiter supports up to six external bus
masters, supporting both fixed priority and rotating priority arbitration
schemes. The part can support both satellite and host PCI configura-
tions, enabling the RC32438 to act as a slave controller for a PCI add-in
Device Overview
The RC32438 is a member of the IDT™ Interprise™ family of PCI
integrated communications processors. It incorporates a high perfor-
mance CPU core and a number of on-chip peripherals. The integrated
processor is designed to transfer information from I/O modules to main
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May 25, 2004
IDT 79RC32438
card application, or as the primary PCI controller in the system. The PCI
interface can be operated synchronously or asynchronously to the other
I/O interfaces on the RC32438 device.
Ethernet Interface
The RC32438 has two Ethernet Channels supporting 10Mbps and
100Mbps speeds to provide a standard media independent interface
(MII) off-chip, allowing a wide range of external devices to be connected
efficiently.
UART Interface
The RC32438 contains two completely separate serial channels
(UARTs) that are compatible with the industry standard 16550 UART.
System Integrity Functions
The RC32438 contains a programmable watchdog timer that gener-
ates NMI when the counter expires and an address space monitor that
reports errors in response to accesses to undecoded address regions.
General Purpose I/O Controller
The RC32438 contains 32 general purpose input/output pins. Each
pin may be used as an active high or active low level interrupt or non-
maskable interrupt input, and each signal may be used as a bit input or
output port.
I
2
C Interface
The standard I2C interface allows the RC32438 to connect to a
number of standard external peripherals for a more complete system
solution. The RC32438 supports both master and slave operations.
Debug Support
The RC32438 supports the industry standard Rev. 2.6 EJTAG inter-
face.
February 4, 2003:
Revised description for EJTAG/JTAG pins in
Table 1. Changed DDRDM[7:0] from input/output to output only in Tables
1 and 2 and Logic Diagram. Added new section, Voltage Sense Signal
Timing, as part of EJTAG description.
March 4, 2003:
In Table 2, removed “pull-up” from PCI pin category
and from GPIO [24] and GPIO[30-26]. In Table 20, changed max. values
for VccSI/O, VccCore, and VccPLL.
July 9, 2003:
In Table 7: changed values for DDRDATA, DDRDM,
and DDRADDR—WEN signals, and deleted old footnote #3 and
changed values in new footnote #3. In Table 8, changed Tdo values.
Changed Figure 7. Changed values in Table 18, Power Consumption.
Removed IPBus Monitor feature which included changes to Tables 1, 2,
21, 24, and 25. Deleted Table 13 which resulted in a re-ordering of
subsequent tables.
March 8, 2004:
Added 300MHz speed grade.
May 25, 2004:
In Table 9, signals MIIxRXCLK and MIIxTXCLK, the
Min and Max values for Thigh/Tlow_9c were changed to 140 and 260
respectively and the Min and Max values for Thigh/Tlow_9d were
changed to 14.0 and 26.0 respectively.
Thermal Considerations
The RC32438 consumes less than 2.7 W peak power. It is guaran-
teed in a ambient temperature range of 0° to +70° C for commercial
temperature devices and - 40° to +85° for industrial temperature
devices.
Revision History
November 7, 2002:
Initial publication. Preliminary Information.
November 15, 2002:
Added footnotes to Tables 5, 9, and 10.
December 12, 2002:
Added Clock Speed parameter to PLL and
Core supply in Table 16.
December 19, 2002:
Release version.
January 13, 2003:
Changed Thermal Considerations to read less
than 2.7W instead of 2.5W, added values to CLK parameter in Table 5,
and revised EJTAG description.
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May 25, 2004
IDT 79RC32438
Pin Description Table
The following table lists the functions of the pins provided on the RC32438. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero
(low) level. All other signals (including clocks, buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.
Signal
System
CLK
Type
Name/Description
I
Master Clock.
This is the master clock input. The processor frequency is a mul-
tiple of this clock frequency. This clock is used as the system clock for all mem-
ory and peripheral bus operations.
External Clock.
This clock is used for all memory and peripheral bus opera-
tions.
Cold Reset.
The assertion of this signal initiates a cold reset. This causes the
processor state to be initialized, boot configuration to be loaded, and the internal
PLL to lock onto the master clock (CLK).
Reset.
The assertion of this bidirectional signal initiates a warm reset. This sig-
nal is asserted by the RC32438 during a warm reset.
EXTCLK
COLDRSTN
O
I
RSTN
I/O
Memory and Peripheral Bus
BDIRN
O
External Buffer Direction.
Memory and peripheral bus external data bus buffer
direction control. If the RC32438 memory and peripheral bus is connected to the
A side of a transceiver, such as an IDT74FCT245, then this pin may be directly
connected to the direction control (e.g., BDIR) pin of the transceiver.
Bus Grant.
This signal is asserted by the RC32438 to indicate that the
RC32438 has relinquished ownership of the memory and peripheral bus.
External Buffer Enable.
This signal provides an output enable control for an
external buffer on the memory and peripheral data bus.
Bus Request.
This signal is asserted by an external device to request owner-
ship of the memory and peripheral bus.
Byte Write Enables.
These signals are memory and peripheral bus byte write
enable signals.
BWEN[0] corresponds to byte lane MDATA[7:0]
BWEN[1] corresponds to byte lane MDATA[15:8]
Chip Selects.
These signals are used to select an external device on the mem-
ory and peripheral bus.
Address Bus.
22-bit memory and peripheral bus address bus.
MADDR[25:22] are available as GPIO alternate functions
Data Bus.
16-bit memory and peripheral data bus. During a cold reset, these
pins function as inputs that are used to load the boot configuration vector.
Output Enable.
This signal is asserted when data should be driven on by an
external device on the memory and peripheral bus.
Read Write.
This signal indicates if the transaction on the memory and periph-
eral bus is a read transaction or a write transaction. A high level indicates a read
from an external device. A low level indicates a write to an external device.
Table 1 Pin Description (Part 1 of 9)
BGN
BOEN
BRN
BWEN[1:0]
O
O
I
O
CSN[5:0]
MADDR[21:0]
MDATA[15:0]
OEN
RWN
O
O
I/O
O
O
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May 25, 2004
IDT 79RC32438
Signal
WAITACKN
Type
I
Name/Description
Wait or Transfer Acknowledge.
When configured as wait, this signal is
asserted during a memory and peripheral bus transaction to extend the bus
cycle. When configured as a transfer acknowledge, this signal is asserted during
a transaction to signal the completion of the transaction.
DDR Bus
DDRADDR[13:0]
DDRBA[1:0]
DDRCASN
DDRCKE
O
O
O
O
DDR Address Bus.
14-bit multiplexed DDR bus address bus. This bus is used
to transfer the addresses to the DDR devices.
DDR Bank Address.
These signals are used to transfer the bank address to the
DDRs.
DDR Column Address Strobe.
This signal is asserted during DDR transac-
tions.
DDR Clock Enable.
The DDR clock enable is asserted during normal DDR
operation. This signal is negated during following a cold reset or during a power
down operation.
DDR Negative DDR clock.
These signals are the negative clock of the differen-
tial DDR clock pair. Two copies of this output are provided to reduce signal load-
ing.
DDR Positive DDR clock.
These signals are the positive clock of the differen-
tial DDR clock pair. Two copies of this output are provided to reduce signal load-
ing.
DDR Chip Selects.
These active low signals are used to select DDR device(s)
on the DDR bus.
DDR Data Bus.
32-bit DDR data bus used to transfer data between the
RC32438 and the DDR devices. Data is transferred on both edges of the clock.
DDR Data Write Enables.
Byte data write enables used to enable specific byte
lanes during DDR writes.
DDRDM[0] corresponds to DDRDATA[7:0]
DDRDM[1] corresponds to DDRDATA[15:8]
DDRDM[2] corresponds to DDRDATA[23:16]
DDRDM[3] corresponds to DDRDATA[31:24]
DDRDM[4] corresponds to DDRDATA[39:32]
DDRDM[5] corresponds to DDRDATA[47:40]
DDRDM[6] corresponds to DDRDATA[55:48]
DDRDM[7] corresponds to DDRDATA[54:56]
(Refer to the DDR Data Bus Multiplexing section in Chapter 7 of the RC32438
User Reference Manual.)
DDR Data Strobes.
DDR byte data strobes used to clock data between DDR
devices and the RC32438. These strobes are inputs during DDR reads and out-
puts during DDR writes.
DDRDQS[0] corresponds to DDRDATA[7:0].
DDRDQS[1] corresponds to DDRDATA[15:8].
DDRDQS[2] corresponds to DDRDATA[23:16].
DDRDQS[3] corresponds to DDRDATA[31:24].
DDR Bus Switch Output Enables.
These pins are used to enable external
data bus switches in systems that support data bus multiplexing.
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