DATASHEET
ISL78233, ISL78234
3A and 4A Compact Synchronous Buck Regulators
The
ISL78233, ISL78234
are highly efficient, monolithic,
synchronous step-down DC/DC converters that can deliver 3A
(ISL78233), or 4A (ISL78234) of continuous output current from
a 2.7V to 5.5V input supply. The devices use current mode control
architecture to deliver a very low duty cycle operation at high
frequency with fast transient response and excellent loop stability.
The ISL78233, ISL78234 integrate a very low ON-resistance
P-channel (35mΩ) high-side FET and N-channel (11mΩ)
low-side FET to maximize efficiency and minimize external
component count. The 100% duty-cycle operation allows less
than 200mV dropout voltage at 4A output current. The
operation frequency of the Pulse Width Modulator (PWM) is
adjustable from 500kHz to 4MHz. The default switching
frequency of 2MHz is set by connecting the FS pin high.
The ISL78233, ISL78234 can be configured for discontinuous
or forced continuous operation at light load. Forced continuous
operation reduces noise and RF interference, while
discontinuous mode provides higher efficiency by reducing
switching losses at light loads.
Fault protection is provided by internal hiccup mode current
limiting during short-circuit and overcurrent conditions. Other
protection, such as overvoltage and over-temperature are also
integrated into the device. A power-good output voltage
monitor indicates when the output is in regulation.
The ISL78233, ISL78234 offers a 1ms Power-Good (PG) timer
at power-up. When in shutdown, the ISL78233, ISL78234
discharges the output capacitor through an internal soft-stop
switch. Other features include internal fixed or adjustable
soft-start and internal/external compensation.
The ISL78233, ISL78234 is available in a 3mmx3mm 16 Ld
Thin Quad Flat Pb-free (TQFN) package and in a 5mmx5mm
16 Ld Wettable Flank Quad Flat No-Lead (WFQFN) package
with an exposed pad for improved thermal performance. The
ISL78233, ISL78234 are rated to operate across the
temperature range of -40°C to +125°C.
FN8359
Rev 7.00
December 4, 2015
Features
• 2.7V to 5.5V input voltage range
• Very low ON-resistance FETs - P-channel 35mΩ and
N-Channel 11mΩ typical values
• High efficiency synchronous buck regulator with up to 95%
efficiency
• -1.2%/1% reference accuracy over temperature/load/line
• Complete BOM with as few as 3 external parts
• Internal soft-start - 1ms or adjustable
• Soft-stop output discharge during disable
• Adjustable frequency from 500kHz to 4MHz - default at
2MHz
• External synchronization up to 4MHz
• Over-temperature, overcurrent, overvoltage and negative
overcurrent protection
• Shared common device pinout allows simplified output
power upgrades over time
• Tiny 3mmx3mm TQFN package
• AEC-Q100 qualified
Applications
• DC/DC POL modules
•
μC/µP,
FPGA and DSP power
• Video processor/SOC power
• Li-ion battery powered devices
• Automotive infotainment power
Related Literature
•
UG015,
“ISL7823xEVAL1Z Evaluation Board User Guide”
•
ISL78235
datasheet.
•
UG062,
“ISL7823xEVAL2Z Evaluation Board User Guide”
100
3.3V
OUT
90
EFFICIENCY (%)
80
1.2V
OUT
70 2.5V
OUT
60
50
40
0.0
1.5V
OUT
1.8V
OUT
0.5
1.0
1.5
2.0
2.5
OUTPUT LOAD (A)
3.0
3.5
4.0
FIGURE 1. EFFICIENCY vs LOAD (2MHz 5V
IN
PFM, T
A
= +25°C)
FN8359 Rev 7.00
December 4, 2015
Page 1 of 20
ISL78233, ISL78234
Pin Configuration
ISL78233, ISL78234
(16 LD TQFN)
TOP VIEW
PHASE
PHASE
14
PHASE
13
VIN
16
15
VIN 1
VDD 2
PG 3
SYNC 4
12
11
10
9
PGND
PGND
SGND
FB
5
6
7
8
FS
EN
SS
Pin Descriptions
PIN NUMBER
1, 16
2
3
4
SYMBOL
VIN
VDD
PG
SYNC
DESCRIPTION
Input supply voltage. Place a minimum of two 22µF ceramic capacitors from VIN to PGND as close as
possible to the IC for decoupling.
Input supply voltage for logic. Connect to VIN pin.
Power-good is an open-drain output. Use a 10kΩ to 100kΩ pull-up resistor connected between VIN and
PG. At power-up or EN HI, PG rising edge is delayed by 1ms upon output reached within regulation.
Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or
ground for PFM mode. Connect to an external function generator for synchronization with the positive
edge trigger. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state in case
of SYNC pin float.
Regulator enable pin. Enable the output when driven to high. Shutdown the chip and discharge output
capacitor when driven to low.
This pin sets the oscillator switching frequency, using a resistor, RFS, from the FS pin to GND. The
frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 2MHz
if FS is connected to VIN.
SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor from
SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC.
The feedback network of the regulator, FB, is the negative input to the transconductance error
amplifier. COMP is the output of the amplifier if COMP not tied to VDD. Otherwise, COMP is
disconnected through a MOSFET for internal compensation. Must connect COMP to VDD in internal
compensation mode. The output voltage is set by an external resistor divider connected to FB. With a
properly selected divider, the output voltage can be set to any voltage between the power rail (reduced
by converter losses) and the 0.6V reference. There is an internal compensation to meet a typical
application. Additional external networks across COMP and SGND might be required to improve the
loop compensation of the amplifier operation.
In addition, the regulator power-good and undervoltage protection circuitry use FB to monitor the
regulator output voltage.
Signal ground
Power ground
Switching node connections. Connect to one terminal of the inductor. This pin is discharged by a 100Ω
resistor when the device is disabled. See
“Functional Block Diagram” on page 5
for more detail.
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as
many vias as possible under the pad connecting to SGND plane for optimal thermal performance.
5
6
EN
FS
7
8, 9
SS
COMP, FB
10
11, 12
13, 14, 15
Exposed Pad
SGND
PGND
PHASE
-
FN8359 Rev 7.00
December 4, 2015
COMP
Page 2 of 20
ISL78233, ISL78234
Ordering Information
PART NUMBER
(Notes
1, 2, 3)
ISL78233ARZ
ISL78233AARZ
ISL78234ARZ
ISL78234AARZ
ISL78233EVAL1Z
ISL78234EVAL1Z
ISL78233EVAL2Z
ISL78234EVAL2Z
NOTES:
1. Add “-T” suffix for 6k unit or “-T7A” suffix for 250 unit tape and reel options. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL78233, ISL78234
For more information on MSL please see techbrief
TB363.
8233
78233A ARZ
8234
78234A ARZ
PART
MARKING
OUTPUT VOLTAGE
(V)
Adjustable
Adjustable
Adjustable
Adjustable
TEMP. RANGE
(°C)
-40 to +125
-40 to +125
-40 to +125
-40 to +125
PACKAGE
(RoHS Compliant)
16 Ld 3x3 TQFN
16 Ld 5x5mm WFQFN
16 Ld 3x3 TQFN
16 Ld 5x5mm WFQFN
PKG.
DWG. #
L16.3x3D
L16.5x5D
L16.3x3D
L16.5x5D
3x3mm TQFN Evaluation Board
3x3mm TQFN Evaluation Board
5x5mm WFQFN Evaluation Board
5x5mm WFQFN Evaluation Board
TABLE 1. KEY DIFFERENCE BETWEEN FAMILY OF PARTS
PART NUMBER
ISL78233
ISL78234
ISL78235
I
OUT
MAX
(A)
3
4
5
FN8359 Rev 7.00
December 4, 2015
Page 3 of 20
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