CY505YC64DT
Clock Generator for Intel
®
Broadwater Chipset
Features
• Compliant to Intel CK505
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz Differential SRC clocks
• 100 MHz Differential LCD clock
• 96 MHz Differential Dot clock
• 48 MHz USB clocks
• 33 MHz PCI clock
• 25 MHz PATA clock
• Buffered Reference Clock 14.318 MHz
Table 1. Output Configuration Table
CPU
x2/x3
SRC
x8/12
PCI REF DOT96 USB_48M
x6
x1
x1
x1
LCD
x1
®
• Low-voltage frequency select input
• I
2
C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V Power supply/0.7V for Diff IOs
•
64-pin TSSOP package
Block Diagram
Pin Configuration
PCI_0/OE#_0/2_A
VDD_PCI
PCI_1/OE#_1/4_A
PCI_2/TME
PCI_3/ FSD*
PCI_4/ SRC5_EN
PCIF_0/ ITP_EN
VSS_PCI
VDD_48
USB_48/ FSA
VSS_48
VDD_IO
SRCT0/DOT96T
SRCC0/DOT96C
VSS_IO
VDD_PLL3
SRCT1/LCDT_100/25M
SRCC1/LCDC_100
VSS_PLL3
VDD_PLL3_IO
SRCT2_SATAT
SRCC2_SATAC
VSS_SRC
SRCT3/OE#_0/2_B
SRCC3/OE#_1/4_B
VDD_SRC_IO
SRCT4
SRCC4
VSS_SRC
SRCT9
SRCC9
SRCC11/OE#_9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK
SDATA
REF0/FSC/TEST_SEL
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
FSB/TEST_MODE
CK_PWRGD/PWRDWN#
VDD_CPU
CPUT0
CPUC0
VSS_CPU
CPUT1
CPUC1
VDD_CPU_IO
IO_VOUT
SRCT8/ CPU2_ITPT
SRCC8/ CPU2_ITPC
VDD_SRC_IO
SRCT7/OE#_8
SRCC7/OE#_6
VSS_SRC
SRCT6
SRCC6
VDD_SRC
SRCT5/ PCI_STOP#
SRCC5/ CPU_STOP#
VDD_SRC_IO
SRCC10
SRCT10
SRCT11/OE#_10
* Internal Pull-Down
CY505YC64DT
...................... Document #: 001-03543 Rev *E Page 1 of 24
400 West Cesar Chavez, Austin, TX 78701
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1+(512) 416-9669
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CY505YC64D
Pin Definitions
Pin No.
Name
1
PCI_0/OE#_0/2_A
2
3
4
VDD_PCI
PCI_1/OE#_1/4_A
PCI_2/TME
Type
Description
I/O, SE 33 MHz clock/3.3V OE# Input mappable via I2C to control either SRC 0 or
SRC 2. Default PCI0
PWR
3.3V Power supply for PCI PLL.
I/O, SE 33 MHz clock/3.3V OE# Input mappable via I2C to control either SRC 1 or
SRC 4. Default PCI1.
I/O, SE 3.3V tolerance input for overclocking enable pin 33 MHz clock.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifica-
tions.
I/O, SE, 3.3V tolerant input for CPU frequency selection/33 MHz clock.
PD
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifica-
tions.
I/O, SE 3.3V tolerant input to enable SRC5/33 MHz clock output.
(sampled on the CK_PWRGD assertion)
1 = SRC5, 0 = CPU_STOP#
I/O, SE 3.3V LVTTL input to enable SRC8 or CPU2_ITP/33 MHz clock output.
PD
(sampled on the CK_PWRGD assertion)
1 = CPU2_ITP, 0 = SRC8
GND
PWR
I/O
Ground for outputs.
3.3V Power supply for outputs and PLL.
3.3V tolerant input for CPU frequency selection/fixed 48 MHz clock output.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifica-
tions.
Ground for outputs.
0.7V Power supply for outputs.
5
PCI_3/FSD
6
PCI_4/SRC5_SEL
7
PCIF_0/ITP_EN
8
9
10
VSS_PCI
VDD_48
USB_48/FSA
11
12
13, 14
15
16
17, 18
19
20
21, 22
23
24, 25
VSS_48
VDD_IO
SRCT0/DOT96T
SRCC0/DOT96C
VSS_IO
VDD_PLL3
SRCT1/LCDT_100/25M
SRCC1/LCDC_100
VSS_PLL3
VDD_PLL3_IO
SRCT/C[2]/SATA
VSS_SRC
SRCT3/OE#_0/2_B
SRCC3/OE#_1/4_B
VDD_SRC_IO
SRCT/C[4]
VSS_SRC
SRCT/C[9]
SRCT11/OE#_10
SRCC11/OE#_9
VDD_SRC_IO
SRCT5/PCI_STOP#
SRCC5/CPU_STOP#
VDD_SRC
GND
PWR
O, DIF 100 MHz Differential serial reference clocks/Fixed 96 MHz clock output.
Selected via I2C default is SRC0.
GND
PWR
Ground for PLL2.
3.3V Power supply for PLL3
O, DIF, 100 MHz Differential serial reference clocks/100 MHz LCD video clock/25 MHz
SE
SATA clock. Default LCD
GND
PWR
GND
I/O,
Dif
PWR
GND
I/O,
Dif
PWR
I/O,
Dif
PWR
Ground for PLL3.
0.7V Power supply for PLL3 outputs.
Ground for outputs.
100-MHz Differential serial reference clocks/3.3V OE#_0/2_B, input,
mappable via I2C to control either SRC 0 or SRC 2/3.3V OE#_1/4_B input,
mappable via I2C to control either SRC 1 or SRC 4. Default SRC3
0.7V power supply for SRC outputs.
Ground for outputs.
100 MHz Differential serial reference clocks/3.3V OE#9 Input controlling
SRC9/3.3V OE#10 Input controlling SRC10. Default SRC11.
0.7V Power supply for SRC outputs.
3.3V tolerant input for stopping PCI and SRC outputs/3.3V tolerant input for
stopping CPU outputs/100 MHz Differential serial reference clocks. Default
SRC5
3.3V Power supply for SRC PLL.
O, DIF 100 MHz Differential serial reference clocks.
26
27, 28
29
30, 31
33, 32
O, DIF 100 MHz Differential serial reference clocks.
O, DIF 100 MHz Differential serial reference clocks.
34, 35, SRCT/C[10]
36
38, 37
O, DIF 100 MHz Differential serial reference clocks.
39
......................Document #: 001-03543 Rev *E Page 2 of 24
CY505YC64D
Pin Definitions
(continued)
Pin No.
Name
41, 40 SRCT/C[6]
42
44, 43
45
47, 46
VSS_SRC
SRCT7/OE#_8
SRCC7/OE#_6
VDD_SRC_IO
SRCT8/CPUT2_ITPT,
SRCC8/CPUC2_ITPC
IO_VOUT
VDD_CPU_IO
CPUT/C[1]
VSS_CPU
Type
Description
O, DIF 100 MHz Differential serial reference clocks.
GND
I/O,
Dif
PWR
Ground for outputs.
100 MHz Differential serial reference clocks/3.3V OE#8 Input controlling
SRC8/3.3V OE#6 Input controlling SRC6. Default SRC7.
0.7V power supply for SRC outputs.
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
O
PWR
Integrated Linear Regulator Control.
0.7V Power supply for CPU outputs.
48
49
51, 50
52
O, DIF Differential CPU clock outputs. Note: CPU1 is the iAMT clock and is on in that
mode.
GND
Ground for outputs.
O, DIF Differential CPU clock outputs. Note: CPU1 is the iAMT clock and is on in that
mode.
PWR
I
3.3V Power supply for CPU PLL.
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, FS_D, SRC5_SEL, and ITP_EN.
After CK_PWRGD (active HIGH) assertion, this pin becomes a real-time input
for asserting power down (active LOW).
3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifica-
tions.
Ground for outputs.
14.318 MHz Crystal input.
3.3V Power supply for outputs and also maintains SMBUS registers during
power-down.
3.3V tolerant input for CPU frequency selection/fixed 14.318 clock output.
Selects test mode if pulled to V
IHFS_C
when CK_PWRGD is asserted HIGH.
Refer to DC Electrical Specifications table for
V
ILFS_C
, V
IMFS_C
, V
IHFS_C
speci-
fications.
SMBus compatible SDATA.
SMBus compatible SCLOCK.
54, 53 CPUT/C[0]
55
56
VDD_CPU
CK_PWRGD/PWRDWN#
57
FSB/TEST_MODE
I
58
59
60
61
62
VSS_REF
XOUT
XIN
VDD_REF
REF0/FSC/TEST_SEL
GND
I
PWR
I/O
O, SE 14.318 MHz Crystal output.
63
64
SMB_DATA
SMB_CLK
I/O
I
......................Document #: 001-03543 Rev *E Page 3 of 24
CY505YC64D
Frequency Select Pin (FSA, FSB, FSC, and FSD)
To achieve host clock frequency selection, apply the appro-
priate logic levels to FS_A, FS_B, FS_C, and FS_D inputs
before VTT_PWRGD# assertion (as seen by the clock synthe-
sizer). When VTT_PWRGD# is sampled LOW by the clock
chip (indicating processor VTT voltage is stable), the clock
chip samples the FS_A, FS_B, FS_C, and FS_D input values.
For all logic levels of FS_A, FS_B, FS_C, FS_D, and FS_E,
VTT_PWRGD# employs a one-shot functionality, in that once
a valid LOW on VTT_PWRGD# has been sampled, all further
VTT_PWRGD#, FS_A, FS_B, FS_C, and FS_D transitions will
be ignored, except in test mode.
Frequency Select Pin (FSA, FSB, FSC, and FSD)
Input Conditions
FSD
FSEL_3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FSC
FSEL_2
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
FSB
FSEL_1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FSA
FSEL_0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
CPU
(MHz)
100
133
166
200
266
333
400
200
100.9
133.9
166.9
200.9
266.9
333.9
400.9
200.9
SRC
(MHz)
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
Output Frequency
SATA
(MHz)
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
DOT96
(MHz)
96
96
96
96
96
96
96
96
96
96
96
96
96
96
96
96
USB
(MHz)
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
PCI
(MHz)
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.4
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
REF
(MHz)
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 2.
The block write and block read protocol is outlined in
Table 3
while
Table 4
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h)
.
Table 2. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
......................Document #: 001-03543 Rev *E Page 4 of 24
CY505YC64D
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
46
....
....
....
....
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Byte Count–8 bits
(Skip this step if I
2
C_EN bit set)
Acknowledge from slave
Data byte 1–8 bits
Acknowledge from slave
Data byte 2–8 bits
Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N–8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
46:39
47
55:48
56
....
....
....
....
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeat start
Slave address–7 bits
Read = 1
Acknowledge from slave
Byte Count from slave–8 bits
Acknowledge
Data byte 1 from slave–8 bits
Acknowledge
Data byte 2 from slave–8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data Byte N from slave–8 bits
NOT Acknowledge
Stop
Block Read Protocol
Description
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeated start
Slave address–7 bits
Read
Acknowledge from slave
Data from slave–8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Control Registers
Byte 0: Control Register 0
Bit
@Pup
Name
Description
......................Document #: 001-03543 Rev *E Page 5 of 24
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