19-0537; Rev 0; 4/06
KIT
ATION
EVALU
BLE
AVAILA
1.8V, Low-Power, 12-Bit, 250Msps
ADC for Broadband Applications
General Description
Features
o
250Msps Conversion Rate
o
Excellent Low-Noise Characteristics
SNR = 66.7dB at f
IN
= 100MHz
SNR = 65.6dB at f
IN
= 250MHz
o
Excellent Dynamic Range
SFDR = 84.7dBc at f
IN
= 100MHz
SFDR = 80dBc at f
IN
= 250MHz
o
Single 1.8V Supply
o
886mW Power Dissipation at f
SAMPLE
= 250Msps
and f
IN
= 100MHz
o
On-Chip Track-and-Hold Amplifier
o
Internal 1.25V-Bandgap Reference
o
On-Chip Selectable Divide-by-2 Clock Input
o
LVDS Digital Outputs with Data Clock Output
o
MAX1215NEVKIT Available
MAX1215N
The MAX1215N is a monolithic, 12-bit, 250Msps ana-
log-to-digital converter (ADC) optimized for outstanding
dynamic performance at high-IF frequencies beyond
300MHz. The product operates with conversion rates
up to 250Msps while consuming only 886mW.
At 250Msps and an input frequency of 100MHz, the
MAX1215N achieves an 84.7dBc spurious-free dynam-
ic range (SFDR) with e6.7dB signal-to-noise ratio (SNR)
that remains flat (within 2dB) for input tones up to
250MHz. This makes it ideal for wideband applications
such as communications receivers, cable-head end
receivers, and power-amplifier predistortion in cellular
base-station transceivers (BTS).
The MAX1215N operates from a single 1.8V power sup-
ply. The analog input is designed for AC-coupled differ-
ential or single-ended operation. The ADC also features a
selectable on-chip divide-by-2 clock circuit that accepts
clock frequencies as high as 500MHz. A low-voltage dif-
ferential signal (LVDS) sampling clock is recommended
for best performance. The converter provides LVDS-com-
patible digital outputs with data format selectable to be
either two’s complement or offset binary.
The MAX1215N is available in a 68-pin QFN package
with exposed paddle (EP) and is specified over the indus-
trial (-40°C to +85°C) temperature range.
See the
Pin-Compatible Versions
table for a complete
selection of 8-bit, 10-bit, and 12-bit high-speed ADCs
in this family.
Ordering Information
PART
MAX1215NEGK-D
MAX1215NEGK+D
TEMP RANGE
PIN-
PACKAGE
PKG
CODE
-40°C to +85°C 68 QFN-EP* G6800-4
-40°C to +85°C 68 QFN-EP* G6800-4
*EP
= Exposed paddle.
+Denotes
lead-free package.
D = Dry pack.
Applications
Base-Station Power-Amplifier Linearization
Cable-Head End Receivers
Wireless and Wired Broadband Communications
Communications Test Equipment
Radar and Satellite Subsystems
MAX1121
MAX1122
MAX1123
MAX1124
MAX1213
MAX1214
MAX1215
MAX1213N
MAX1214N
PART
RESOLUTION
(BITS)
8
10
10
10
12
12
12
12
12
12
Pin-Compatible Versions
SPEED
GRADE
(Msps)
250
170
210
250
170
210
250
170
210
250
ON-CHIP
BUFFER
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Pin Configuration appears at end of data sheet.
MAX1215N
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1.8V, Low-Power, 12-Bit, 250Msps
ADC for Broadband Applications
MAX1215N
ABSOLUTE MAXIMUM RATINGS
AV
CC
to AGND ......................................................-0.3V to +2.1V
OV
CC
to OGND .....................................................-0.3V to +2.1V
AV
CC
to OV
CC
.......................................................-0.3V to +2.1V
AGND to OGND ....................................................-0.3V to +0.3V
Analog Inputs to AGND ...........................-0.3V to (AV
CC
+ 0.3V)
All Digital Inputs to AGND........................-0.3V to (AV
CC
+ 0.3V)
REFIO, REFADJ to AGND ........................-0.3V to (AV
CC
+ 0.3V)
All Digital Outputs to OGND ....................-0.3V to (OV
CC
+ 0.3V)
ESD on All Pins (Human Body Model).............................±2000V
Current into Any Pin..........................................................±50mA
Continuous Power Dissipation (T
A
= +70°C, multilayer board)
68-Pin QFN-EP (derate 41.7mW/°C above +70°C)....3333mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering,10s) ..................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
CC
= OV
CC
= 1.8V, AGND = OGND = 0, f
SAMPLE
= 250MHz, differential clock input drive, 0.1µF capacitor on REFIO, internal ref-
erence, digital output pins differential R
L
= 100Ω. Limits are for T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at
T
A
= +25°C.) (Note 1)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity (Note 2)
Differential Nonlinearity (Note 2)
Transfer Curve Offset
Offset Temperature Drift
ANALOG INPUTS (INP, INN)
Full-Scale Input Voltage Range
Full-Scale Range Temperature
Drift
Common-Mode Input Voltage
Differential Input Capacitance
Differential Input Resistance
Full-Power Analog Bandwidth
REFERENCE (REFIO, REFADJ)
Reference Output Voltage
Reference Temperature Drift
REFADJ Input High Voltage
SAMPLING CHARACTERISTICS
Maximum Sampling Rate
Minimum Sampling Rate
Clock Duty Cycle
Aperture Delay
Aperture Jitter
t
AD
t
AJ
f
SAMPLE
f
SAMPLE
Set by clock-management circuit
Figures 5, 11
Figure 11
250
20
40 to 60
620
0.15
MHz
MHz
%
ps
ps
RMS
V
REFADJ
Used to disable the internal reference
AV
CC
- 0.3
V
REFIO
REFADJ = AGND
1.18
1.25
90
1.30
V
ppm/°C
V
V
CM
C
IN
R
IN
FPBW
Internally self-biased
V
FS
1250
1385
±60
0.7
2.5
1.8
700
mV
P-P
ppm/°C
V
pF
kΩ
MHz
INL
DNL
V
OS
f
IN
= 10MHz
No missing codes
(Note 2)
12
-3
-1.0
-3.5
±20
±0.8
±0.4
+3
+1.3
+3.5
Bits
LSB
LSB
mV
µV/°C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
________________________________________________________________________________________
1.8V, Low-Power, 12-Bit, 250Msps
ADC for Broadband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= OV
CC
= 1.8V, AGND = OGND = 0, f
SAMPLE
= 250MHz, differential clock input drive, 0.1µF capacitor on REFIO, internal ref-
erence, digital output pins differential R
L
= 100Ω. Limits are for T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at
T
A
= +25°C.) (Note 1)
PARAMETER
CLOCK INPUTS (CLKP, CLKN)
Differential Clock Input Amplitude
Clock Input Common-Mode
Voltage Range
Clock Differential Input
Resistance
Clock Differential Input
Capacitance
R
CLK
C
CLK
(Note 3)
Internally self-biased
200
500
1.15 ±0.25
11 ±25%
5
mV
P-P
V
kΩ
pF
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX1215N
DYNAMIC CHARACTERISTICS (at A
IN
= -1dBFS)
f
IN
= 10MHz
Signal-to-Noise Ratio
SNR
f
IN
= 100MHz
f
IN
= 200MHz
f
IN
= 250MHz
f
IN
= 10MHz
Signal-to-Noise
and Distortion
SINAD
f
IN
= 100MHz
f
IN
= 200MHz
f
IN
= 250MHz
f
IN
= 10MHz
Spurious-Free
Dynamic Range
SFDR
f
IN
= 100MHz
f
IN
= 200MHz
f
IN
= 250MHz
f
IN
= 10MHz
Worst Harmonics
(HD2 or HD3)
f
IN
= 100MHz
f
IN
= 200MHz
f
IN
= 250MHz
Two-Tone Intermodulation
Distortion
Differential Output Voltage
Output Offset Voltage
TTIMD
f
IN1
= 99MHz at A
IN1
= -7dBFS,
f
IN2
= 101MHz at A
IN2
= -7dBFS
R
L
= 100Ω
R
L
= 100Ω
280
1.11
70
70
63.5
63.3
64.5
64.3
67
66.7
66.1
65.6
66.8
66.4
65.9
65.4
86
84.7
83.4
80
-86
-84.7
-83.4
-80
-86.9
dBc
-70
-70
dBc
dBc
dB
dB
LVDS DIGITAL OUTPUTS (D0P/N–D11P/N, ORP/N)
|V
OD
|
OV
OS
440
1.37
mV
V
_______________________________________________________________________________________
3
1.8V, Low-Power, 12-Bit, 250Msps
ADC for Broadband Applications
MAX1215N
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= OV
CC
= 1.8V, AGND = OGND = 0, f
SAMPLE
= 250MHz, differential clock input drive, 0.1µF capacitor on REFIO, internal ref-
erence, digital output pins differential R
L
= 100Ω. Limits are for T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at
T
A
= +25°C.) (Note 1)
PARAMETER
Digital Input-Voltage Low
Digital Input-Voltage High
TIMING CHARACTERISTICS
CLK-to-Data Propagation Delay
CLK-to-DCLK Propagation Delay
DCLK-to-Data Propagation Delay
LVDS Output Rise Time
LVDS Output Fall Time
Output Data Pipeline Delay
POWER REQUIREMENTS
Analog Supply Voltage Range
Digital Supply Voltage Range
Analog Supply Current
Digital Supply Current
Analog Power Dissipation
Power-Supply Rejection Ratio
(Note 4)
AV
CC
OV
CC
I
AVCC
I
OVCC
P
DISS
PSRR
f
IN
= 100MHz
f
IN
= 100MHz
f
IN
= 100MHz
Offset
Gain
1.7
1.7
1.8
1.8
428
64
886
1.7
4.5
1.9
1.9
480
74
965
V
V
mA
mA
mW
mV/V
%FS/V
t
PDL
t
CPDL
t
RISE
t
FALL
t
LATENCY
Figure 5
Figure 5
1.47
20% to 80%, C
L
= 5pF
20% to 80%, C
L
= 5pF
Figure 5
2.23
3.77
1.54
155
145
11
1.63
ns
ns
ns
ps
ps
Clock
cycles
SYMBOL
V
IL
V
IH
0.8 x AV
CC
CONDITIONS
MIN
TYP
MAX
0.2 x AV
CC
UNITS
V
V
LVCMOS DIGITAL INPUTS (CLKDIV,
T/B)
t
CPDL
- t
PDL
Figure 5 (Note 3)
Note 1:
T
A
≥
+25°C guaranteed by production test, T
A
< +25°C guaranteed by design and characterization. Typical values are at
T
A
= +25°C
Note 2:
Static linearity and offset parameters are computed from an endpoint curve fit.
Note 3:
Parameter guaranteed by design and characterization: T
A
= -40°C to +85°C.
Note 4:
PSRR is measured with both analog and digital supplies connected to the same potential.
4
________________________________________________________________________________________
1.8V, Low-Power, 12-Bit, 250Msps
ADC for Broadband Applications
Typical Operating Characteristics
(AV
CC
= OV
CC
= 1.8V, AGND = OGND = 0, f
SAMPLE
= 250MHz, A
IN
= -1dBFS, see each TOC for detailed information on test condi-
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential R
L
= 100Ω, T
A
= +25°C.)
FFT PLOT
(8192-POINT DATA RECORD)
MAX1215N toc01
MAX1215N
FFT PLOT
(8192-POINT DATA RECORD)
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
f
SAMPLE
= 250MHz
f
IN
= 65.033MHz
A
IN
= -1.008dBFS
SNR = 67dB
SINAD = 66.9dB
THD = -83.6dBc
SFDR = 87dBc
HD2 = -87dBc
HD3 = -81.8dBc
3
4
5
2
MAX1215N toc02
FFT PLOT
(8192-POINT DATA RECORD)
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
f
SAMPLE
= 250MHz
f
IN
= 199.249MHz
A
IN
= -1.004dBFS
SNR = 66dB
SINAD = 65.9dB
THD = -81dBc
SFDR = 82.7dBc
HD2 = -90.9dBc
HD3 = -82.7dBc
3
2
MAX1215N toc03
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
3
2
4
5
AMPLITUDE (dBS)
f
SAMPLE
= 250MHz
f
IN
= 11.566MHz
A
IN
= -0.982dBFS
SNR = 67.1dB
SINAD = 66.953dB
THD = -82.5dBc
SFDR = 84.7dBc
HD2 = -94.9dBc
HD3 = -84.7dBc
0
0
5
4
20
40
60
80
100
ANALOG INPUT FREQUENCY (MHz)
120
20
40
60
80
100
ANALOG INPUT FREQUENCY (MHz)
120
20
40
60
80
100
ANALOG INPUT FREQUENCY (MHz)
120
FFT PLOT
(8192-POINT DATA RECORD)
MAX1215N toc04
TWO-TONE IMD PLOT
(32,768-POINT DATA RECORD)
MAX1215N toc05
SNR/SINAD vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 250MHz, A
IN
= -1dBFS)
SNR
67
SNR/SINAD (dB)
64
61
58
55
52
0
50
100
150
200
f
IN
(MHz)
250
300
MAX1215N toc06
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
AMPLITUDE (dBFS)
AMPLITUDE (dBS)
2
35
4
f
SAMPLE
= 250MHz
f
IN
= 248.627MHz
A
IN
= -0.933dBFS
SNR = 65.4dB
SINAD = 65.185dB
THD = -78dBc
SFDR = 82.7dBc
HD2 = -82.7dBc
HD3 = -83.1dBc
0
f
SAMPLE
= 250MHz
f
IN1
= 99MHz
f
IN2
= 101MHz
IMD = -86dBc
70
-25
-50
SINAD
-75
-100
-125
20
40
60
80
100
ANALOG INPUT FREQUENCY (MHz)
120
0
25
50
75
100
125
ANALOG INPUT FREQUENCY (MHz)
SFDR vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 250MHz, A
IN
= -1dBFS)
MAX1215N toc07
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 250MHz, AIN = -1dBFS)
-52
-56
-60
-64
-68
-72
-76
-80
-84
-88
-92
-96
-100
0
50
70
65
60
55
50
45
40
35
30
25
20
15
10
MAX1215N toc08
SNR/SINAD vs. ANALOG INPUT AMPLITUDE
(f
SAMPLE
= 250MHz, f
IN
= 65.033MHz)
MAX1215N toc09
90
85
SFDR (dBc)
80
SNR/SINAD (dB)
HD2/HD3 (dBc)
SNR
SINAD
75
HD2
70
HD3
100
150
200
f
IN
(MHz)
250
300
65
0
50
100
150
200
f
IN
(MHz)
250
300
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
ANALOG INPUT AMPLITUDE (dBFS)
0
_______________________________________________________________________________________
5
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