SERIAL FLASH MEMORY WITH 166/104MHZ MULTI I/O SPI &
QUAD I/O QPI DTR INTERFACE
DATA SHEET
IS25LP256D
IS25WP256D
256Mb
SERIAL FLASH MEMORY WITH 166MHZ MULTI I/O SPI &
QUAD I/O QPI DTR INTERFACE
FEATURES
Industry Standard Serial Interface
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IS25LP256D: 256Mbit/32Mbyte
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IS25WP256D: 256Mbit/32Mbyte
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3 or 4 Byte Addressing Mode
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Supports Standard SPI, Fast, Dual, Dual
I/O, Quad, Quad I/O, SPI DTR, Dual I/O
DTR, Quad I/O DTR, and QPI
-
Software & Hardware Reset
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Supports Serial Flash Discoverable
Parameters (SFDP)
High Performance Serial Flash (SPI)
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80MHz Normal Read
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Up to166Mhz Fast Read:
-166MHz at Vcc=2.7V to 3.6V
(1)
-133MHz at Vcc=2.3V to 3.6V
-104MHz at Vcc=1.65V to 1.95V
-
Up to 80MHz DTR (Dual Transfer Rate)
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Equivalent Throughput of 664 Mb/s
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Selectable Dummy Cycles
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Configurable Drive Strength
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Supports SPI Modes 0 and 3
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More than 100,000 Erase/Program Cycles
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More than 20-year Data Retention
Flexible & Efficient Memory Architecture
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Chip Erase with Uniform Sector/Block
Erase (4/32/64 Kbyte)
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Program 1 to 256 Byte per Page
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Program/Erase Suspend & Resume
Efficient Read and Program modes
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Low Instruction Overhead Operations
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Continuous Read 8/16/32/64 Byte
Burst Wrap
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Selectable Burst Length
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QPI for Reduced Instruction Overhead
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AutoBoot Operation
Low Power with Wide Temp. Ranges
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Single Voltage Supply
IS25LP: 2.30V to 3.60V
IS25WP: 1.65V to 1.95V
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7.5 mA Active Read Current
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10 µA Standby Current
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1 µA Deep Power Down
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Temp Grades:
Extended: -40°C to +105°C
Auto Grade (A3): 40°C to +125°C
Advanced Security Protection
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Software and Hardware Write Protection
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Advanced Sector/Block Protection
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Top/Bottom Block Protection
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Power Supply Lock Protection
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4x256 Byte Dedicated Security Area
with OTP User-lockable Bits
-
128 bit Unique ID for Each Device
(Call Factory)
Industry Standard Pin-out & Packages
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M =16-pin SOIC 300mil
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L = 8-contact WSON 8x6mm
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G = 24-ball TFBGA (4x6 ball array)
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H = 24-ball TFBGA (5x5 ball array)
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KGD (Call Factory)
Note:
1. 166MHz at Mode 0 , and 133MHz at Mode 3
Integrated Silicon Solution, Inc.- www.issi.com
Rev.A
06/29/2017
2
IS25LP256D
IS25WP256D
GENERAL DESCRIPTION
The IS25LP256D and IS25WP256D Serial Flash memory offers a versatile storage solution with high flexibility
and performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash is for systems
that require limited space, a low pin count, and low power consumption. The device is accessed through a 4-wire
SPI Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable
(CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions).
The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock frequencies
of up to 166MHz allow for equivalent clock rates of up to 664MHz (166MHz x 4) which equates to 83Mbytes/s of
data throughput. The IS25xP series of Flash adds support for DTR (Double Transfer Rate) commands that transfer
addresses and read data on both edges of the clock. These transfer rates can outperform 16-bit Parallel Flash
memories allowing for efficient memory access to support XIP (execute in place) operation.
The memory array is organized into programmable pages of 256 bytes. This family supports page program mode
where 1 to 256 bytes of data are programmed in a single command. QPI (Quad Peripheral Interface) supports 2-
cycle instruction further reducing instruction times. Pages can be erased in groups of 4Kbyte sectors, 32Kbyte
blocks, 64Kbyte blocks, and/or the entire chip. The uniform sector and block architecture allows for a high degree
of flexibility so that the device can be utilized for a broad variety of applications requiring solid data retention.
GLOSSARY
Standard SPI
In this operation, a 4-wire SPI Interface is utilized, consisting of Serial Data Input (SI), Serial Data Output (SO),
Serial Clock (SCK), and Chip Enable (CE#) pins. Instructions are sent via the SI pin to encode instructions,
addresses, or input data to the device on the rising edge of SCK. The SO pin is used to read data or to check the
status of the device. This device supports SPI bus operation modes (0,0) and (1,1).
Mutil I/O SPI
Multi-I/O operation utilizes an enhanced SPI protocol to allow the device to function with Dual Output, Dual Input
and Output, Quad Output, and Quad Input and Output capability. Executing these instructions through SPI mode
will achieve double or quadruple the transfer bandwidth for READ and PROGRAM operations.
Quad I/O QPI
The device enables QPI protocol by issuing an “Enter QPI mode (35h)” command. The QPI mode uses four IO
pins for input and output to decrease SPI instruction overhead and increase output bandwidth. SI and SO pins
become bidirectional IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3 respectively during QPI mode.
Issuing an “Exit QPI (F5h) command will cause the device to exit QPI mode. Power Reset or Hardware/Software
Reset can also return the device into the standard SPI mode.
DTR
In addition to SPI and QPI features, the device also supports Fast READ DTR operation. Fast READ DTR operation
allows high data throughput while running at lower clock frequencies. Fast READ DTR operation uses both rising
and falling edges of the clock for address inputs, and data outputs, resulting in reducing input and output cycles
by half.
Programmable drive strength and Selectable burst setting.
The device offers programmable output drive strength and selectable burst (wrap) length features to increase the
efficiency and performance of READ operation. The driver strength and burst setting features are controlled by
setting the Read Registers. A total of six different drive strengths and four different burst sizes (8/16/32/64 Byte)
are available for selection.
Integrated Silicon Solution, Inc.- www.issi.com
Rev.A
06/29/2017
3
IS25LP256D
IS25WP256D
TABLE OF CONTENTS
FEATURES ........................................................................................................................................................... 2
GENERAL DESCRIPTION ................................................................................................................................... 3
TABLE OF CONTENTS ........................................................................................................................................ 4
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