CAT5270
Dual Digitally Programmable
Potentiometers (DPP) with
256 Taps & I
2
C Compatible
Interface
Description
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The CAT5270 is a volatile 256−tap by two channels, digitally
programmable potentiometer (DPP) with an I
2
C compatible interface.
Each DPP consists of a linear taper series of resistive elements
connected between two externally accessible end points. The tap
points between each resistive element are connected to the wiper
outputs with CMOS switches. On power up the wiper position goes to
mid scale.
The CAT5270 can be used as a potentiometer or as a two terminal,
variable resistor. It is available in a 14−lead TSSOP package operating
over the industrial temperature range (−40°C to 85°C).
Features
1
TSSOP−14
Y SUFFIX
CASE 948AM
PIN CONNECTION
1
A0
V
CC
R
LO
R
HO
R
WO
A2
SDA
TSSOP−14 (Y)
(Top View)
A3
SCL
GND
R
W1
R
H1
R
L1
A1
•
•
•
•
•
•
•
•
•
•
Two Linear Taper Digitally Programmable Potentiometers
256 Resistor Taps per Potentiometer
End to End Resistance 50 kW, 100 kW
I
2
C Compatible Interface
Low Wiper Resistance 75
W
(typ.)
2.5 V to 5.5 V Operation
Standby Current Less than 1
mA
Power On to Mid Scale
14−lead TSSOP Package
Industrial Temperature Range
R
H0
R
H1
SDA
SCL
I
2
C COMPAT-
IBLE
INTERFACE
256−POSITION
DECODE
CONTROL
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
R
W0
R
W1
A0
A1
A2
A3
CONTROL
LOGIC
R
L0
R
L1
Figure 1. Functional Diagram
©
Semiconductor Components Industries, LLC, 2012
May, 2012
−
Rev. 4
1
Publication Order Number:
CAT5270/D
CAT5270
Pin Description
SCL: Serial Clock
Table 1. PIN DESCRIPTION
Pin #
TSSOP−14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Name
A0
V
CC
R
L0
R
H0
R
W0
A2
SDA
A1
R
L1
R
H1
R
W1
GND
SCL
A3
Function
Device Address, LSB
Supply Voltage
Low Reference Terminal for
Potentiometer 0
High Reference Terminal for
Potentiometer 0
Wiper Terminal for Potentiometer 0
Device Address
Serial Data Input/Output
Device Address
Low Reference Terminal for
Potentiometer 1
High Reference Terminal for
Potentiometer 1
Wiper Terminal for Potentiometer 1
Ground
Bus Serial Clock
Device Address
The CAT5270 serial clock input pin is used to clock all
data transfers into or out of the device.
SDA: Serial Data
The CAT5270 bidirectional serial data pin is used to
transfer data into and out of the device. The SDA pin is an
open drain output and can be wire−OR’d with the other open
drain or open collector I/Os.
A0, A1, A2, A3: Device Address Inputs
These inputs set the device address when addressing
multiple devices. A total of sixteen devices can be addressed
on a single bus. A match in the slave address must be made
with the address input in order to initiate communication
with the CAT5270.
The two sets of R
H
and R
L
pins are equivalent to the
terminal connections on a mechanical potentiometer.
The R
W
pins are equivalent to the wiper terminal of a
mechanical potentiometer.
Device Operation
The CAT5270 is two resistor arrays integrated with an I
2
C
compatible interface and two 8−bit wiper control registers.
Each resistor array contains 255 separate resistive elements
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical
potentiometer (R
H
and R
L
). The tap positions between and
at the ends of the series resistors are connected to the output
R
W
: Wiper
R
H
, R
L
: Resistor End Points
wiper terminals (R
W
) by a CMOS transistor switch. Only
one tap point for each potentiometer is connected to its wiper
terminal at a time and is determined by the value of the wiper
control register. Data can be read or written to the wiper
control register via the I
2
C compatible interface. Also, the
device can be instructed to operate in an “increment/
decrement” mode.
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CAT5270
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Temperature Under Bias
Storage Temperature
Voltage on Any Pin with Respect to V
SS
(Note 1)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25°C)
Lead Soldering Temperature (10 sec)
Wiper Current
Ratings
−55
to +125
−65
to +150
−2.0
to +V
CC
+ 2.0
−2.0
to +6.0
1.0
300
±6
Units
°C
°C
V
V
W
°C
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is
−0.5
V. During transitions, inputs may undershoot to
−2.0
V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5 V, which may overshoot to V
CC
+2.0 V for periods of less than 20 ns.
Table 3. RECOMMENDED OPERATING CONDITIONS
Parameters
V
CC
Industrial Temperature
Ratings
+2.5 to +5.5
−40
to +85
Units
V
°C
Table 4. POTENTIOMETER CHARACTERISTICS
(V
CC
= +2.5 V to +5.5 V, unless otherwise specified.)
Limits
Symbol
R
POT
R
POT
Parameter
Potentiometer Resistance (100 kW)
Potentiometer Resistance (50 kW)
Potentiometer Resistance Tolerance
R
POT
Matching
Power Rating
I
W
R
W
R
W
V
TERM
Wiper Current
Wiper Resistance
Wiper Resistance
Voltage on any R
H
or R
L
Pin
Resolution
Absolute Linearity (Note 4)
Relative Linearity (Note 5)
TC
RPOT
TC
RATIO
C
H
/C
L
/C
W
fc
Temperature Coefficient of R
POT
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Frequency Response
R
w(n)(actual)
−
R
(n)(expected)
(Note 7)
R
w(n+1)
– R
[w(n)+LSB]
(Note 7)
(Note 3)
(Note 3)
(Note 3)
R
POT
= 50 kW (Note 3)
10/10/25
0.4
±100
20
I
W
=
±3
mA @ V
CC
= 3 V
I
W
=
±3
mA @ V
CC
= 5 V
V
SS
= 0 V
V
SS
0.4
±1
±0.2
200
75
25°C, each pot
Test Conditions
Min
Typ
100
50
±20
1
50
±3
300
150
V
CC
Max
Units
kW
kW
%
%
mW
mA
W
W
V
%
LSB
(Note 6)
LSB
(Note 6)
ppm/°C
ppm/°C
pF
MHz
2. Latch−up protection is provided for stresses up to 100 mA on address and data pins from
−1
V to V
CC
+1 V.
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
5. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.
It is a measure of the error in step size.
6. LSB = R
TOT
/ 255 or (R
H
−
R
L
) / 255, single pot
7. n = 0, 1, 2, ..., 255
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CAT5270
Table 5. DC OPERATING CHARACTERISTICS
(V
CC
= +2.5 V to +5.5 V, unless otherwise specified.)
Symbol
I
CC
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL1
Parameter
Power Supply Current
Standby Current (V
CC
= 5.0 V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= 2.5 V)
I
OL
= 3 mA
Test Conditions
f
SCL
= 400 kHz, SDA = Open
V
CC
= 5.5 V, Inputs = GND
V
IN
= GND or V
CC
, SDA = Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
−1
V
CC
x 0.7
Min
Max
1
5
10
10
V
CC
x 0.3
V
CC
+ 1.0
0.4
Units
mA
mA
mA
mA
V
V
V
Table 6. CAPACITANCE
(T
A
= 25°C, f = 1.0 MHz, V
CC
= 5 V)
Symbol
C
I/O
(Note 8)
C
IN
(Note 8)
Test
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3, SCL, WP)
Conditions
V
I/O
= 0 V
V
IN
= 0 V
Max
8
6
Units
pF
pF
Table 7. AC CHARACTERISTICS
2.5 V – 5.5 V
Symbol
f
SCL
T
I
(Note 8)
t
AA
t
BUF
(Note 8)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
(Note 8)
t
F
(Note 8)
t
SU:STO
t
DH
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the bus must be free before a new transmission can start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
0.6
100
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
Parameter
Min
Max
400
200
1
Units
kHz
ns
ms
ms
ms
ms
ms
ms
ns
ns
ms
ns
ms
ns
Table 8. POWER UP TIMING
(Notes 8 and 9)
Symbol
t
PUR
t
PUW
Power−up to Read Operation
Power−up to Write Operation
Parameter
Max
1
1
Units
ms
ms
Table 9. WIPER TIMING
Symbol
t
WRPO
t
WRL
Parameter
Wiper Response Time After Power Supply Stable
Wiper Response Time After Instruction Issued
Max
10
10
Units
ms
ms
8. This parameter is tested initially and after a design or process change that affects the parameter.
9. t
PUR
and t
PUW
are delays required from the time V
CC
is stable until the specified operation can be initiated.
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CAT5270
t
F
t
LOW
SCL
t
HIGH
t
LOW
t
R
t
SU:STA
SDA IN
t
HD:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
AA
SDA OUT
t
DH
t
BUF
Figure 2. Bus Timing
Serial Bus Protocol
The following defines the features of the I
2
C compatible
interface protocol:
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock is high
will be interpreted as a START or STOP condition.
The device controlling the transfer is a master, typically a
processor or controller, and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations.
Therefore, the CAT5270 will be considered a slave device
in all applications.
START Condition
After the Master sends a START condition and the slave
address byte, the CAT5270 monitors the bus and responds
with an acknowledge (on the SDA line) when its address
matches the transmitted slave address.
Slave Address Byte
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH (see Figure 3). The CAT5270 monitors
the SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
The most significant four bits of the slave address are a
device type identifier. These bits for the CAT5270 are fixed
at 0101[B] (refer to Figure 5).
The next four bits, A3
−
A0, are the internal slave address
and must match the physical device address which is defined
by the state of the A3
−
A0 input pins for the CAT5270 to
successfully continue the command sequence. Only the
device which slave address matches the incoming device
address sent by the master executes the instruction. The A3
−
A0 inputs can be actively driven by CMOS input signals
or tied to V
CC
or V
SS
.
Acknowledge
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition (see Figure 3). All
operations must end with a STOP condition.
Device Addressing
The bus Master begins a transmission by sending a
START condition. The Master then sends the Slave Addres
Byte which contains the address of the particular slave
device it is requesting. The four most significant bits of the
8−bit slave address are fixed as 0101 for the CAT5270. The
next four significant bits (A3, A2, A1, A0) are the device
address bits and define which device the Master is accessing
(see Figure 5). Up to sixteen devices may be individually
addressed by the system. Typically, +5 V (V
CC
) and ground
are hard−wired to these pins to establish the device’s
address.
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data (see Figure 4).
The CAT5270 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8−bit
byte.
When the CAT5270 is in a READ mode it transmits 8 bits
of data, releases the SDA line, and monitors the line for an
acknowledge. Once it receives this acknowledge, the
CAT5270 will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data transmission
and waits for a STOP condition.
If the device has been selected with an IN/DEC operation
it will no longer responds with acknoleadge as the received
data it is not in a byte format.
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