CY7C6431x
CY7C6434x
CY7C6435x
enCoRe™ V Full Speed USB Controller
enCoRe™ V Full Speed USB Controller
Features
Powerful Harvard-architecture processor
❐
M8C processor speeds running up to 24 MHz
❐
Low power at high processing speeds
❐
Interrupt controller
❐
3.0 V to 5.5 V operating voltage without USB
❐
Operating voltage with USB enabled:
• 3.15 V to 3.45 V when supply voltage is around 3.3 V
• 4.35 V to 5.25 V when supply voltage is around 5.0 V
❐
Commercial temperature range: 0 °C to +70 °C
❐
Industrial temperature range: –40 °C to +85 °C
■
Flexible on-chip memory
❐
Up to 32 KB flash program storage:
• 50,000 erase and write cycles
• Flexible protection modes
❐
Up to 2048 bytes SRAM data storage
❐
In-system serial programming (ISSP)
■
Complete development tools
❐
Free development tool PSoC Designer™
❐
Full-featured, in-circuit emulator and programmer
❐
Full-speed emulation
❐
Complex breakpoint structure
❐
128-KB trace memory
■
Precision, programmable clocking
❐
Crystal-less oscillator with support for an external crystal or
resonator
❐
Internal ±5.0% 6, 12, or 24 MHz main oscillator (IMO):
• 0.25% accuracy with oscillator lock to USB data, no
external components required
• Internal low-speed oscillator (ILO) at 32 kHz for watchdog
and sleep. The frequency range is 19 to 50 kHz with a
32-kHz typical value
■
■
■
■
Programmable pin configurations
❐
Up to 36 general purpose I/O (GPIO) depending on package.
❐
25 mA sink current on all GPIO
• 60mA total sink current on Even port pins and 60 mA total
sink current on Odd port pins
• 120 mA total sink current on all GPIOs
❐
Pull-up, High Z, open drain, CMOS drive modes on all GPIO
❐
CMOS drive mode A -5 mA source current on ports 0 and 1
and 1 mA on ports 2, 3, and 4
• 20 mA total source current on all GPIOs
❐
Low dropout voltage regulator for Port 1 pins:
• Programmable to output 3.0, 2.5, or 1.8 V
❐
Selectable, regulated digital I/O on Port 1
❐
Configurable input threshold for Port 1
❐
Hot-swappable Capability on Port 1
Full-Speed USB (12 Mbps)
❐
Eight unidirectional endpoints
❐
One bidirectional control endpoint
❐
USB 2.0-compliant: TID# 40000893
❐
Dedicated 512 bytes buffer
❐
No external crystal required
Additional system resources
❐
Configurable communication speeds
2
❐
I C slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• Implementation requires no clock stretching
• Implementation during sleep modes with less than 100
A
• Hardware address detection
❐
SPI master and SPI slave:
• Configurable between 46.9 kHz and 12 MHz
❐
Three 16-bit timers
❐
10-bit ADC used to monitor battery voltage or other signals
with external components
❐
Watchdog and sleep timers
❐
Integrated supervisory circuit
Port 2
Port 1
Port 0
Prog. LDO
enCoRe V Block Diagram
enCoRe V
CORE
Port 4
Port 3
System Bus
SRAM
2048 Bytes
Interrupt
Controller
SROM
8K/16K/32K Flash
Sleep and
Watchdog
CPU Core
(M8C)
6/12/24 MHz Internal Main Oscillator
ADC
3 16-Bit
Timers
I2C Slave/SPI
Master-Slave
POR and LVD
System Resets
Full
Speed
USB
SYSTEM RESOURCES
Errata:
For information on silicon errata, see
“Errata”
on page 35. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 001-12394 Rev. *U
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 27, 2017
CY7C6431x
CY7C6434x
CY7C6435x
Contents
Functional Overview ........................................................ 3
The enCoRe V Core .................................................... 3
Full-Speed USB ........................................................... 3
10-bit ADC ................................................................... 4
SPI ............................................................................... 4
I2C Slave ..................................................................... 5
Additional System Resources ..................................... 6
Getting Started .................................................................. 6
Application Notes ........................................................ 6
Development Kits ........................................................ 6
Training ....................................................................... 6
CYPros Consultants .................................................... 6
Solutions Library .......................................................... 6
Technical Support ....................................................... 6
Development Tools .......................................................... 7
PSoC Designer Software Subsystems ........................ 7
Designing with PSoC Designer ....................................... 8
Select User Modules ................................................... 8
Configure User Modules .............................................. 8
Organize and Connect ................................................ 8
Generate, Verify, and Debug ....................................... 8
Pin Information ................................................................. 9
16-pin part pinout ........................................................ 9
Pin Definitions ............................................................. 9
32-pin part pinout ...................................................... 10
Pin Definitions ........................................................... 10
48-pin Part Pinout ...................................................... 11
Pin Definitions ........................................................... 11
Register Reference ......................................................... 13
Register Conventions .................................................... 13
Register Mapping Tables ............................................... 13
Electrical Specifications ................................................ 16
Absolute Maximum Ratings ....................................... 17
Operating Temperature ............................................. 17
DC Electrical Characteristics ..................................... 18
AC Electrical Characteristics ..................................... 22
Package Diagram ............................................................ 29
Packaging Dimensions .............................................. 29
Package Handling ..................................................... 31
Thermal Impedances ................................................. 31
Capacitance on Crystal Pins ..................................... 31
Solder Reflow Peak Temperature ............................. 31
Ordering Information ...................................................... 32
Ordering Code Definitions ......................................... 33
Acronyms ........................................................................ 34
Document Conventions ................................................. 34
Units of Measure ....................................................... 34
Numeric Naming ........................................................ 34
Errata ............................................................................... 35
CY7C643xx Errata Summary .................................... 35
Document History Page ................................................. 37
Sales, Solutions, and Legal Information ...................... 41
Worldwide Sales and Design Support ....................... 41
Products .................................................................... 41
PSoC® Solutions ...................................................... 41
Cypress Developer Community ................................. 41
Technical Support ..................................................... 41
Document Number: 001-12394 Rev. *U
Page 2 of 41
CY7C6431x
CY7C6434x
CY7C6435x
Functional Overview
The enCoRe V family of devices are designed to replace multiple
traditional full-speed USB microcontroller system components
with one, low cost single-chip programmable component.
Communication peripherals (I
2
C/SPI), a fast CPU, Flash
program memory, SRAM data memory, and configurable I/O are
included in a range of convenient pinouts.
The architecture for this device family, as illustrated in the
enCoRe V Block Diagram on page 1,
consists of two main areas:
the CPU core and the system resources. Depending on the
enCoRe V package, up to 36 GPIO are also included.
This product is an enhanced version of Cypress’s successful full
speed-USB peripheral controllers. Enhancements include faster
CPU at lower voltage operation, lower current consumption,
twice the RAM and Flash, hot-swappable I/Os, I
2
C hardware
address recognition, new very low current sleep mode, and new
package options.
TEN
TD
RECEIVERS
PDN
RD
Figure 1. USB Transceiver Regulator
VOLTAGE
REGULATOR
5V 3.3V
1.5K
5K
PS2 Pull Up
DP
DM
TRANSMITTER
DPO
RSE0
DMO
The enCoRe V Core
The enCoRe V Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO and
ILO. The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four-MIPS, 8-bit Harvard
architecture microprocessor.
During USB operation, the CPU speed can be set to any setting.
Be aware that USB throughput decreases with a decrease in
CPU speed. For maximum throughput, the CPU clock should be
made equal to the system clock. The system clock must be
24 MHz for USB operation.
System resources provide additional capability, such as a
configurable I
2
C slave and SPI master-slave communication
interface and various system resets supported by the M8C.
At the enCoRe V system level, the full-speed USB system
resource interfaces to the rest of the enCoRe V by way of the
M8C’s register access instructions and to the outside world by
way of the two USB pins. The SIE supports nine endpoints
including a bidirectional control endpoint (endpoint 0) and eight
unidirectional data endpoints (endpoints 1 to 8). The
unidirectional data endpoints are individually configurable as
either IN or OUT.
Low value series resistors R
EXT
(22
Ω)
must be added externally
to the D+ and D– lines to meet the driving impedance
requirement for full-speed USB.
The USB Serial Interface Engine (SIE) allows the enCoRe V
device to communicate with the USB host at full speed data rates
(12 Mb/s). The SIE simplifies the interface to USB traffic by
automatically handling the following USB processing tasks
without firmware intervention:
■
■
■
■
■
■
■
Full-Speed USB
The enCoRe V USB system resource adheres to the USB 2.0
Specification for full speed devices operating at 12 Mb/second
with one upstream port and one USB address. enCoRe V USB
consists of these components:
■
■
■
■
Serial interface engine (SIE) block.
PSoC memory arbiter (PMA) block.
512 bytes of dedicated SRAM.
A full-speed USB Transceiver with internal regulator and two
dedicated USB pins.
Translates the encoded received data and formats the data to
be transmitted on the bus.
Generates and checks cyclical redundancy checks (CRCs).
Incoming packets failing checksum verification are ignored.
Checks addresses. Ignores all transactions not addressed to
the device.
Sends appropriate ACK/NAK/Stall handshakes.
Identifies token type (SETUP, IN, OUT) and sets the
appropriate token bit once a valid token in received.
Identifies Start-of-Frame (SOF) and saves the frame count.
Sends data to or retrieves data from the USB SRAM, by way
of the PSoC Memory Arbiter (PMA).
Document Number: 001-12394 Rev. *U
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CY7C6431x
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CY7C6435x
Firmware is required to handle various parts of the USB
interface. The SIE issues interrupts after key USB events to
direct firmware to appropriate tasks:
■
■
■
■
■
input mux or the temperature sensor with an input voltage range
of 0 V to V
REFADC
.
In the ADC only configuration (the ADC MUX selects the Analog
mux bus, not the default temperature sensor connection), an
external voltage can be connected to the input of the modulator
for voltage conversion. The ADC is run for a number of cycles
set by the timer, depending upon the desired resolution of the
ADC. A counter counts the number of trips by the comparator,
which is proportional to the input voltage. The Temp Sensor block
clock speed is 36 MHz and is divided down to 1 to 12 MHz for
ADC operation.
Fill and empty the USB data buffers in USB SRAM.
Enable PMA channels appropriately.
Coordinate enumeration by decoding USB device requests.
Suspend and resume coordination.
Verify and select data toggle values.
10-bit ADC
The ADC on enCoRe V device is an independent block with a
state machine interface to control accesses to the block. The
ADC is housed together with the temperature sensor core and
can be connected to this or the Analog mux bus. As a default
operation, the ADC is connected to the temperature sensor
diodes to give digital values of the temperature.
Figure 2. ADC System Performance Block Diagram
V
IN
SPI
The serial peripheral interconnect (SPI) 3-wire protocol uses
both edges of the clock to enable synchronous communication
without the need for stringent setup and hold requirements.
Figure 3. Basic SPI Configuration
SPI Master
SPI Slave
Data is output by
Data is registered at the
both the Master
input of both devices on the
and Slave on
opposite edge of the clock.
one edge of the
clock.
SCLK
MOSI
MISO
TEMP SENSOR/ ADC
TEMP
DIODES
ADC
A device can be a master or slave. A master outputs clock and
data to the slave device and inputs slave data. A slave device
inputs clock and data from the master device and outputs data
for input to the master. Together, the master and slave are
essentially a circular Shift register, where the master generates
the clocking and initiates data transfers.
A basic data transfer occurs when the master sends eight bits of
data, along with eight clocks. In any transfer, both master and
slave transmit and receive simultaneously. If the master only
sends data, the received data from the slave is ignored. If the
master wishes to receive data from the slave, the master must
send dummy bytes to generate the clocking for the slave to send
data back.
Figure 4. SPI Block Diagram
SYSTEM BUS
INTERFACE BLOCK
COMMAND/ STATUS
SPI Block
MOSI,
MISO
SCLK
DATA_IN DATA_OUT
CLK_IN
SYSCLK
CLK_OUT
INT
MOSI,
MISO
SCLK
Interface to the M8 C
( Processor ) Core
SS_
Registers
The ADC User Module contains an integrator block and one
comparator with positive and negative input set by the MUXes.
The input to the integrator stage comes from the analog global
CONFIGURATION[7:0]
TRANSMIT[7:0]
CONTROL[7:0]
RECEIVE[7:0]
Document Number: 001-12394 Rev. *U
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SPI configuration register (SPI_CFG) sets master/slave
functionality, clock speed, and interrupt select. SPI control
register (SPI_CR) provides four control bits and four status bits
for device interfacing and synchronization.
The SPIM hardware has no support for driving the Slave Select
(SS_) signal. The behavior and use of this signal is dependent
on the application and enCoRe V device and, if required, must
be implemented in firmware.
There is an additional data input in the SPIS, Slave Select (SS_),
which is an active low signal. SS_ must be asserted to enable
the SPIS to receive and transmit. SS_ has two high level
functions:
■
■
■
■
■
■
Interrupt or polling CPU interface.
Support for clock rates of up to 400 kHz.
7- or 10-bit addressing (through firmware support).
SMBus operation (through firmware support).
Support for 7-bit hardware address compare.
Flexible data buffering schemes.
A “no bus stalling” operating mode.
A low power bus monitoring mode.
Enhanced features of the I
2
C Slave Enhanced Module include:
■
■
■
■
To allow for the selection of a given slave in a multi-slave
environment.
To provide additional clocking for TX data queuing in SPI modes
0 and 1.
I
2
C Slave
The I
2
C slave enhanced communications block is a
serial-to-parallel processor, designed to interface the enCoRe V
device to a two-wire I
2
C serial communications bus. To eliminate
the need for excessive CPU intervention and overhead, the block
provides I
2
C-specific support for status detection and generation
of framing bits. By default, the I
2
C slave enhanced module is
firmware compatible with the previous generation of I
2
C slave
functionality. However, this module provides new features that
are configurable to implement significant flexibility for both
internal and external interfacing. The basic I
2
C features include:
■
■
The I
2
C block controls the data (SDA) and the clock (SCL) to the
external I
2
C interface through direct connections to two
dedicated GPIO pins. When I
2
C is enabled, these GPIO pins are
not available for general purpose use. The enCoRe V CPU
firmware interacts with the block through I/O register reads and
writes, and firmware synchronization is implemented through
polling and/or interrupts.
In the default operating mode, which is firmware compatible with
previous versions of I
2
C slave modules, the I
2
C bus is stalled
upon every received address or byte, and the CPU is required to
read the data or supply data as required before the I
2
C bus
continues. However, this I
2
C Slave Enhanced module provides
new data buffering capability as an enhanced feature. In the
EZI
2
C buffering mode, the I
2
C slave interface appears as a
32-byte RAM buffer to the external I
2
C master. Using a simple
predefined protocol, the master controls the read and write
pointers into the RAM. When this method is enabled, the slave
never stalls the bus. In this protocol, the data available in the
RAM (this is managed by the CPU) is valid.
Slave, transmitter, and receiver operation.
Byte processing for low CPU overhead.
Figure 5. I
2
C Block Diagram
I2C Plus
Slave
I2C Core
SDA_IN
I2C Basic
Configuration
I2C_CFG
I2C_SCR
I2C_DR
Buffer Module
CPU Port
I2C_BUF
System Bus
To/From
GPIO
Pins
SCL_IN
SDA_OUT
SCL_OUT
I2C_EN
32 Byte RAM
HW Addr Cmp
I2C_ADDR
Buffer Ctl
I2C_BP
SYSCLK
STANDBY
Plus Features
I2C_XCFG
I2C_XSTAT
I2C_CP
MCU_BP
MCU_CP
Document Number: 001-12394 Rev. *U
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