DATASHEET
LOW EMI CLOCK GENERATOR
Description
The MK1709 generates a low EMI output clock from a clock
input. The part is designed to dither the LCD interface clock
for flat panel graphics controllers. The device uses IDT’s
proprietary mix of analog and digital Phase Locked Loop
(PLL) technology to spread the frequency spectrum of the
output, thereby reducing the frequency amplitude peaks by
several dB.
The MK1709 offers centered spread from a high speed
clock input. Refer to the MK1714-01/02 for a crystal input
and the widest selection of input frequencies and
multipliers.
IDT offers many other clocks for computers and computer
peripherals. Consult us when you need to remove crystals
and oscillators from your board.
MK1709
Features
•
Packaged in 8-pin SOIC (MK1709S) and in 8-pin TSSOP
(MK1709AG)
•
•
•
•
•
Pb-free package
Provides a spread spectrum output clock
Supports flat panel controllers
Guaranteed to +85° C operation
Accepts a clock input, provides same frequency dithered
output
•
Good for all VGA modes from 40 to 167 MHz
•
Peak reduction by 7dB - 14dB typical on 3rd - 19th odd
harmonics
•
•
•
•
Low EMI feature can be disabled
Includes power-down
Operating voltage of 3.3 V
Advanced, low-power CMOS process
Block Diagram
VDD
S0
S1
S2
Low EMI Enable
PLL Clock
Synthesis
and Spread
Spectrum
Circuitry
Input
Buffer
Clock Out
ICLK
GND
IDT™
LOW EMI CLOCK GENERATOR
1
MK1709
REV M 051310
MK1709
LOW EMI CLOCK GENERATOR
SSCG
Pin Assignment
ICLK
VDD
GND
CLK
1
2
3
4
8
7
6
5
S2
S1
S0
LEE
Spread Percentage and Direction
Select Table
S2
Pin 8
(1709S)
Pin 6
(1709AG)
0
0
0
S1
Pin 7
(1709S)
Pin 5
(1709AG)
0
0
0
S0
Pin 6
(1709S)
Pin 4
(1709AG)
0
M
1
Frequency
Spread
Range
Percentage
(%)
8-pin SOIC (MK1709S)
40-50
40-50
40-50
(MK1709S)
25-50
(MK1709AG)
40-50
(MK1709S)
25-50
(MK1709AG)
40-50
50 -100
50 -100
50 -100
Power Down
50 -100
50 -100
100-165
100-165
100-165
100-165
100-165
100-165
Power Down
±0.9
±0.7
±0.8
GND
CLK
LEE
S0
1
2
3
4
8
7
6
5
VDD
ICLK
S2
S1
0
M
0
±0.6
8-pin TSSOP (MK1709AG)
0
0
0
0
0
1
1
1
1
1
1
1
1
1
M
M
1
1
1
0
0
0
M
M
M
1
1
1
M
1
0
M
1
0
M
1
0
M
1
0
M
1
±1.1
±0.6
±0.7
±0.8
—
±0.9
±1.1
±0.7
±0.6
±1.1
±1.35
±0.8
±0.9
—
0 = connect to GND
M = unconnected (floating) has internal Pull up resistor to
VDD and is considered as a 1 state
1 = connect directly to VDD
IDT™
LOW EMI CLOCK GENERATOR
2
MK1709
REV M 051310
MK1709
LOW EMI CLOCK GENERATOR
SSCG
Pin Descriptions
(MK1709S)
Pin
Number
Pin
Name
Pin Type
Pin Description
1
2
3
4
5
6
7
8
ICLK
VDD
GND
CLK
LEE
S0
S1
S2
Input
Power
Power
Output
Input
Input
Input
Input
Connect to graphics input clock.
Connect to +3.3 V.
Connect to ground.
Spread spectrum clock output per table above.
Low EMI enable. Turns on spread spectrum when high. Internal pull-up resistor.
Function select 0 input. Selects spread amount and direction per table above.
Internal mid-level.
Function select 1 input. Selects spread amount and direction per table above.
Internal mid-level.
Function select 2 input. Selects spread amount and direction per table above.
Pin Descriptions
(MK1709AG)
Pin
Number
Pin
Name
Pin Type
Pin Description
1
2
3
4
5
6
7
8
GND
CLK
LEE
S0
S1
S2
ICLK
VDD
Power
Output
Input
Input
Input
Input
Input
Power
Connect to ground.
Spread spectrum clock output per table above.
Low EMI enable. Turns on spread spectrum when high. Internal pull-up resistor.
Function select 0 input. Selects spread amount and direction per table above.
Internal mid-level.
Function select 1 input. Selects spread amount and direction per table above.
Internal mid-level.
Function select 2 input. Selects spread amount and direction per table above.
Connect to graphics input clock.
Connect to +3.3 V.
IDT™
LOW EMI CLOCK GENERATOR
3
MK1709
REV M 051310
MK1709
LOW EMI CLOCK GENERATOR
SSCG
External Components
The MK1709 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD and GND on pins 2 and 3 for the MK1709S,
or pins 1 and 8 for the MK1709AG. Place the capacitor as
close to these pins as possible. For optimum device
performance, the decoupling capacitor should be mounted
on the component side of the PCB. Avoid the use of vias in
the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock output and the load
is over 1 inch, series termination should be used. To series
terminate a 50Ω trace (a commonly used trace impedance),
place a 33Ω resistor in series with the clock line, as close to
the clock output pin as possible. The nominal impedance of
the clock output is 20Ω
.
Select Pin Operation
The S1, S0 select pins are 2-level, meaning they have three
separate states to make the selections shown in the table on
page 2.
PCB layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via.
2) Place a 33Ω series termination resistor (if needed) close
to the clock output to minimize EMI.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
MK1709. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
IDT™
LOW EMI CLOCK GENERATOR
4
MK1709
REV M 051310
MK1709
LOW EMI CLOCK GENERATOR
SSCG
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1709. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range. Typical values are at 25° C.
Item
Supply Voltage, VDD (referenced to GND)
All Inputs and Outputs (referenced to GND)
Ambient Operating Temperature
Storage Temperature
Soldering Temperature (maximum of 10 seconds)
5V
Rating
-0.5 V to VDD+0.5 V
0 to +85° C
-65 to +150° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.135
Typ.
Max.
+85
+3.6
Units
°
C
V
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V,
Ambient Temperature 0 to +85° C
Parameter
Operating Voltage
Supply Current (MK1709S)
Supply Current (MK1709AG)
Input High Voltage (ICLK)
Input High Voltage (S1, S0)
Input High Voltage (other inputs)
Input Low Voltage (ICLK)
Input Low Voltage
Output High Voltage (CMOS)
Output High Voltage
Output Low Voltage
Input Capacitance
Symbol
VDD
IDD
IDD
IDD
V
IH
V
IH
V
IH
V
IL
V
IL
V
OH
V
OH
V
OL
C
IN
Conditions
No load, at 3.3 V
No load, 50M
No load, 150M
Min.
3.135
Typ.
20
13
23
Max.
3.465
Units
V
mA
µA
V
V
V
(VDD/2)+1
VDD-0.5
2
VDD/2
VDD/2
I
OH
= -4mA
I
OH
= -12 mA
I
OL
= 12 mA
S0, S1, S2, LEE pins
7
VDD-0.4
2.4
(VDD/2)-1
0.5
V
V
V
V
0.4
V
pF
IDT™
LOW EMI CLOCK GENERATOR
5
MK1709
REV M 051310
嵌入式系统
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