DATASHEET
TW2867C
4-Channel Video Decoders and Audio Codecs For
Security Applications
The TW2867 includes four high quality
NTSC/PAL/SECAM video decoders that convert
analog composite video signal to digital
component YCbCr data for security applications.
Each channel contains 10 bit ADC and proprietary
clamp and gain controllers and utilizes 4H comb
filter for separating luminance & chrominance to
reduce cross noise artifacts. The TW2867 adopts
the image enhancement techniques, such as IF
compensation filter, CTI and programmable
peaking. The TW2867 also includes audio CODEC,
which has five audio Analog-to-Digital converters
and one Digital-to-Analog converter. A built-in audio
controller can generate digital outputs for
recording/mixing and accepts digital input for
playback.
FN8257
Rev. 0.00
February 9, 2012
Programmable audio sample rate that covers
popular frequencies of 8/16/32/44.1/48kHz
Supports a two-wire serial host interface
Integrated clock PLL for 108MHz clock output.
Ultra low power consumption (Typical
431.88mW)
128 pin LQFP package
Features
Accepts all NTSC(M/4.43) /
PAL(B/D/G/H/I/K/L/M/N/60)/SECAM
standards with auto detection
Integrated four video analog anti-aliasing filters
and 10 bit CMOS ADCs
High performance adaptive 4H comb filters for
all NTSC/PAL standards
IF compensation filter for improvement of color
demodulation
Color Transient Improvement (CTI)
Automatic white peak control
Programmable hue, saturation, contrast,
brightness and sharpness
Proprietary fast video locking system for non-
realtime application
Supports the standard ITU-R BT.656 format or
time multiplexed output with 54/108MHz
Provides simultaneous four channel Full D1 and
CIF time-multiplexed outputs with 54MHz.
Integrated five audio ADCs and one audio DAC
Provides multi-channel audio mixed analog
output
Supports I2S/DSP Master/Slave interface for
record output and playback input
PCM 8/16 bit and u-Law/A-Law 8bit for audio
word length
FN8257 Rev. 0.00
February 9, 2012
Page 1 of 138
TW2867C
Block Diagram
MUX
VIN1B
AIN1
ADC
ADC
ADC
ADC
Decimation Filter
MPP
Interface
BT.656
Interface
VIN1A
4H Comb
Video Decoder
VD1[7:0]
VD2[7:0]
VD3[7:0]
VD4[7:0]
MPP1
MPP2
MPP3
MPP4
CLKPOn
XTO
XTI
CLKNOn
SCLK
SDAT
IRQ
ACLKR
ASYNR
ADATR
ADATM
ACLKP
ASYNP
ADATP
MUX
VIN2A
VIN2B
AIN2
ADC
ADC
4H Comb
Video Decoder
Decimation Filter
MUX
VIN3A
VIN3B
AIN3
ADC
ADC
4H Comb
Video Decoder
Decimation Filter
ADC
ADC
MUX
VIN4A
VIN4B
AIN4
ADC
ADC
4H Comb
Video Decoder
I2S
Interface
ADC
ADC
Decimation Filter
AIN5
ADC
Decimation Filter
AOUT
DAC
Interpolation Filter
Ordering Information
PART NUMBER
(NOTE 1)
TW2867-QLC1-CR
NOTE:
Host
Interface
Clock PLL
Clock
Generator
ADC
ADC
PART
MARKING
TW2867 QLC1-CR
PACKAGE
(Pb-free)
128 Ld LQFP
PKG.
DWG. #
Q128.14x14
1.
These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die
attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and
compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-
free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8257 Rev. 0.00
February 9, 2012
Page
2
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TW2867C
0x07(CH1)/0x17(CH2)/0x27(CH3)/0x37(CH4) – Cropping
Register, High ........................................................................ 61
0x08(CH1)/0x18(CH2)/0x28(CH3)/0x38(CH4) – Vertical
Delay Register, Low.............................................................. 61
0x09(CH1)/0x19(CH2)/0x29(CH3)/0x39(CH4) – Vertical
Active Register, Low ............................................................. 61
0x0A(CH1)/0x1A(CH2)/0x2A(CH3)/0x3A(CH4) – Horizontal
Delay Register, Low.............................................................. 61
0x0B(CH1)/0x1B(CH2)/0x2B(CH3)/0x3B(CH4) – Horizontal
Active Register, Low ............................................................. 62
0x0C(CH1)/0x1C(CH2)/0x2C(CH3)/0x3C(CH4) –
Macrovision Detection .......................................................... 62
0x0D(CH1)/0x1D(CH2)/0x2D(CH3)/0x3D(CH4) – Chip
STATUS II.............................................................................. 62
0x0E(CH1)/0x1E(CH2)/0x2E(CH3)/0x3E(CH4) – Standard
Selection................................................................................. 63
0x0F(CH1)/0x1F(CH2)/0x2F(CH3)/0x3F(CH4) – Standard
Recognition............................................................................ 64
0xE4(CH1)/0xE7(CH2)/0xEA(CH3)/0xED(CH4) – Vertical
Scaling Register, Low ........................................................... 64
0xE5(CH1)/0xE8(CH2)/0xEB(CH3)/0xEE(CH4) – Scaling
Register, High ........................................................................ 64
0xE6(CH1)/0xE9(CH2)/0xEC(CH3)/0xEF(CH4) – Horizontal
Scaling Register, Low ........................................................... 64
0xA4(CH1)/0xA5(CH2)/0xA6(CH3)/0xA7(CH4) – ID
Detection Control................................................................... 65
0xC4(CH1)/0xC5(CH2)/0xC6(CH3)/0xC7(CH4) – H monitor....... 65
0x80 – Software Reset Control Register.......................................... 65
0x81 – Analog Control Register........................................................ 66
0x82 – Analog Control Reister2........................................................ 66
0x83 – Control Register I ................................................................... 67
0x84 – Color Killer Hysteresis Control Register............................... 67
0x85 – Vertical Sharpness ................................................................ 67
0x86 – Coring Control Register......................................................... 68
0x87 – Clamping Gain....................................................................... 68
0x88 – Individual AGC Gain.............................................................. 68
0x8A – White Peak Threshold .......................................................... 68
0x8B– Clamp level ............................................................................. 68
0x8C– Sync Amplitude...................................................................... 69
0x8D – Sync Miss Count Register.................................................... 69
0x8E – Clamp Position Register....................................................... 69
0x8F – Vertical Control I..................................................................... 69
0x90 – Vertical Control II.................................................................... 70
0x91 – Color Killer Level Control....................................................... 70
0x92 – Comb Filter Control................................................................ 70
0x93 – Luma Delay and H Filter Control.......................................... 70
0x94 – Miscellaneous Control I......................................................... 70
0x95 – LOOP Control Register......................................................... 71
0x96 – Miscellaneous Control II ........................................................ 71
0x97 – CLAMP MODE...................................................................... 72
0x98 – HSLOWCTL .......................................................................... 72
0x99 – HSBEGIN............................................................................... 72
0x9A – HSEND .................................................................................. 73
0x9B – OVSDLY................................................................................ 73
0x9C – OVSEND............................................................................... 73
0x9D – HBLEN................................................................................... 73
0x9E – NOVID.................................................................................... 74
0x9F(CH1)/0x67(CH2)/0x68(CH3)/0x69(CH4) – Clock
Output Delay Control Register ............................................. 75
0xA8 ~0xA9 – Horizontal Scaler Pre-filter Control Register ........... 75
0xA8 – Horizontal Scaler Pre-filter Control Register........................ 75
0xA9 – Horizontal Scaler Pre-filter Control Register........................ 76
Video AGC Control ............................................................................ 76
0xAA – Video AGC Control............................................................... 76
0xAB – Video AGC Control............................................................... 77
0xAC – Video AGC Control .............................................................. 77
0xAD – Video AGC Control .............................................................. 77
0xAE – Video AGC Control............................................................... 77
0xAF – Vertical Peaking Level Control............................................. 78
0xB0 – Vertical Peaking Level Control ............................................. 78
Table of Contents
Pin Diagram ...................................................................................... 5
Pin Descriptions .............................................................................. 6
Analog Video/Audio Interface Pins ..................................................... 6
Digital Video/Audio Interface Pins....................................................... 7
System Control Pins .............................................................................. 8
Power and Ground Pins........................................................................ 9
Functional Description ................................................................. 10
Video Input Formats............................................................................. 10
Analog Frontend ................................................................................... 11
Decimation Filter................................................................................. 12
Automatic Gain Control and Clamping............................................ 13
Sync Processing................................................................................... 13
Y/C Separation....................................................................................... 13
Color Decoding ..................................................................................... 15
Chrominance Demodulation............................................................. 15
ACC (Automatic Color gain control) ................................................. 16
Chrominance Processing ................................................................... 16
Chrominance Gain, Offset and Hue Adjustment ............................ 16
CTI (Color Transient Improvement).................................................. 16
Luminance Processing ....................................................................... 16
Video Cropping ..................................................................................... 17
VDELAY + VACTIVE < Total number of lines per field.........................
17
Video Scaler ........................................................................................... 18
Output Format ....................................................................................... 21
ITU-R BT.656 Format........................................................................ 21
Two Channel ITU-R BT.656 Time-multiplexed Format with
54MHz.................................................................................... 22
Four Channel CIF Time-multiplexed Format with 54MHz ............. 23
Four Channel D1 Time-division-multiplexed Format with
108MHz ................................................................................. 25
Output Enabling Act ........................................................................... 27
Video Output Channel Selection ...................................................... 27
Extra Sync Output.............................................................................. 27
Audio Codec .......................................................................................... 30
Audio Clock Master/Slave mode ...................................................... 32
Audio Detection .................................................................................. 32
Multi-Chip Operation .......................................................................... 32
Serial Audio Interface......................................................................... 35
Playback Input .................................................................................... 35
Record Output .................................................................................... 36
Mix Output........................................................................................... 37
Audio Clock Slave Mode Data Output Timing ................................ 38
ACLKP/ASYNP Slave Mode Data Input Timing............................. 40
Audio Clock Generation .................................................................... 42
Audio Clock Auto Setup .................................................................... 44
Host Interface ................................................................................. 45
Serial Interface ....................................................................................... 45
Interrupt Interface.................................................................................. 46
Squared Pixel Mode Operation.......................................................... 46
Clock PLL ............................................................................................... 47
Control Register .................................................................................... 48
Register Map ...................................................................................... 48
Register Descriptions .......................................................................... 59
0x00(CH1)/0x10(CH2)/0x20(CH3)/0x30(CH4) – Video
Status Register...................................................................... 59
0x01(CH1)/0x11(CH2)/0x21(CH3)/0x31(CH4) –
BRIGHTNESS Control Register ......................................... 59
0x02(CH1)/0x12(CH2)/0x22(CH3)/0x32(CH4) –
CONTRAST Control Register ............................................. 59
0x03(CH1)/0x13(CH2)/0x23(CH3)/0x33(CH4) –
SHARPNESS Control Register........................................... 60
0x04(CH1)/0x14(CH2)/0x24(CH3)/0x34(CH4) – Chroma (U)
Gain Register......................................................................... 60
0x05(CH1)/0x15(CH2)/0x25(CH3)/0x35(CH4) – Chroma (V)
Gain Register......................................................................... 60
0x06(CH1)/0x16(CH2)/0x26(CH3)/0x36(Ch4) – Hue Control
Register.................................................................................. 60
FN8257 Rev. 0.00
February 9, 2012
Page
3
of 138
TW2867C
0xB1 – NOVIDMODE ....................................................................... 79
Audio ADC Digital Input Offset Control ............................................ 79
0xB3 – Audio ADC Digital Input Offset Control .............................. 79
0xB4 – Audio ADC Digital Input Offset Control ............................... 80
0xB5 – Audio ADC Digital Input Offset Control ............................... 80
0xB6 – Audio ADC Digital Input Offset Control ............................... 80
0xB7 – Audio ADC Digital Input Offset Control ............................... 80
0x75 – Audio ADC Digital Input Offset Control............................... 80
0x76 – Audio ADC Digital Input Offset Control................................ 80
Analog Audio ADC Digital Output Value.......................................... 81
0xB8 – Analog Audio ADC Digital Output Value............................. 81
0xB9 – Analog Audio ADC Digital Output Value............................. 81
0xBA – Analog Audio ADC Digital Output Value ............................ 81
0xBB – Analog Audio ADC Digital Output Value ............................ 81
0xBC – Analog Audio ADC Digital Output Value............................ 81
0x77 – Analog Audio ADC Digital Output Value ............................ 81
0x78 – Analog Audio ADC Digital Output Value ............................. 82
Adjusted Analog Audio ADC Digital Input Value............................. 82
0xBD – Adjusted Analog Audio ADC Digital Input Value............... 82
0xBE – Adjusted Analog Audio ADC Digital Input Value ............... 82
0xBF – Adjusted Analog Audio ADC Digital Input Value................ 82
0xC0 – Adjusted Analog Audio ADC Digital Input Value................ 82
0xC1 – Adjusted Analog Audio ADC Digital Input Value................ 83
0x79 – Adjusted Analog Audio ADC Digital Input Value ............... 83
0x7A – Adjusted Analog Audio ADC Digital Input Value................ 83
MPP Pin Output Mode Control......................................................... 84
0xC8 – MPP Pin Output Mode Control............................................ 84
0xC9 – MPP Pin Output Mode Control............................................ 85
0xCA – Video Channel Output Control............................................ 86
0xCB – Four Channel CIF Time-multiplexed Format..................... 87
0xCC – 2nd Channel Selection ........................................................ 88
0xCD – 1st Channel Selection.......................................................... 89
0xCE – Analog Power Down Control............................................... 90
0xCF – Serial Mode Control.............................................................. 90
0xD0, 0xD1, 0x7F - Analog Audio Input Gain ................................. 91
0xD2 – Number of Audio to be Recorded ....................................... 92
0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA –
Sequence of Audio to be Recorded.................................... 93
0xDB –Master Control ....................................................................... 94
u-Law/A-Law Output and Mix Mute Control .................................... 95
0xDC –u-Law/A-Law Output and Mix Mute Control....................... 95
0x7E – MIX_MUTE_A5 .................................................................... 95
Mix Ratio Value .................................................................................. 96
0x72 – Mix Ratio Value...................................................................... 96
0xDD – Mix Ratio Value .................................................................... 96
0xDE – Mix Ratio Value .................................................................... 97
0xDF – Analog Audio Output Gain.................................................. 97
0xE0 – Mix Output Selection............................................................ 98
Audio Detection Period and Audio Detection Threshold................ 99
0xE1 – Audio Detection Period and Audio Detection
Threshold............................................................................... 99
0xE2 – Audio Detection Threshold................................................ 100
0xE3 – Audio Detection Threshold................................................ 100
Audio Clock Increment .................................................................... 100
0xF0 – Audio Clock Increment....................................................... 100
0xF1 – Audio Clock Increment....................................................... 100
0xF2 – Audio Clock Increment....................................................... 100
Audio Clock Number........................................................................ 101
0xF3 – Audio Clock Number.......................................................... 101
0xF4 – Audio Clock Number.......................................................... 101
0xF5 – Audio Clock Number.......................................................... 101
0xF6 – Serial Clock Divider ............................................................ 101
0xF7 – Left/Right Clock Divider...................................................... 101
0xF8 – Audio Clock Control ........................................................... 102
0xF9 – Video Miscellaneous Function Control............................. 103
Output Enable Control and Clock Output Control......................... 104
0xFA – Output Enable Control and Clock Output Control........... 104
0x6A – Clock Output Control ......................................................... 105
0x6B – Clock Output Control ......................................................... 105
0x6C – Output Enable Control and Clock Output Control........... 106
Clock Polarity Control.......................................................................106
0xFB – Clock Polarity Control ........................................................106
0x6D – Clock Polarity Control ........................................................107
Enable Video and Audio Detection.................................................108
0xFC – Enable Video and Audio Detection..................................108
0x73 – Enable Video and Audio Detection ...................................108
Status of Video and Audio Detection..............................................109
0xFD – Status of Video and Audio Detection ...............................109
0x74 – Status of Video and Audio Detection ................................109
Device ID and Revision ID Flag......................................................109
0xFE – Device ID and Revision ID Flag........................................109
0xFF – Device ID and Revision ID Flag........................................110
0x60 – Clock PLL Control...............................................................110
0x61 – 108MHz Clock Select.........................................................111
0x65 – VIDEO Bus Tri-state Control .............................................111
0x66 – Optional Clock Output ........................................................112
0x6E – Reserved.............................................................................113
0x6F – Reserved.............................................................................113
0x70 – Audio Clock Control............................................................113
0x71 – Digital Audio Input Control...................................................114
ADATM I2S Output Select ..............................................................115
0x7B – ADATM I2S Output Select .................................................115
0x7C – ADATM I2S Output Select.................................................116
AIN5 Record Output ........................................................................116
0x7D – AIN5 Record Output ...........................................................116
0x89 – Audio Fs Mode Control .......................................................117
0xB2 – VDLOSS Output .................................................................117
0x50 – Audio DAC Gain Control.....................................................118
0x51 – Audio DAC Low Pass Bias Control ...................................119
0x52 – Audio DAC LPF and Bias Control......................................120
0x53 – Audio DAC Test Control .....................................................121
0x54 – Audio ADC Control..............................................................122
0x58 – AVDS Status(Test Purpose only) ......................................122
0x59 – AVDS Power Control(Test Purpose only).........................123
0x5A – VSAVE.................................................................................123
0x5B– Video Output Pin Drive ........................................................124
0x5C– Video Output Pin Drive........................................................124
0x5D – CH2 Miscellaneous Control II on BGCTL=1....................125
0x5E – CH3 Miscellaneous Control II on BGCTL=1 ....................125
0x5F – CH4 Miscellaneous Control II on BGCTL=1.....................126
Electrical Information .................................................................. 127
Absolute Maximum Ratings .............................................................127
Recommended Operating Conditions ...........................................127
DC Electrical Parameters ..................................................................128
XTI and Video Data/Sync Timing .....................................................129
Digital Serial Audio Interface Timing...............................................130
Serial Host Interface Timing..............................................................131
Video Decoder Parameter 1..............................................................132
Video Decoder Parameter 2..............................................................133
Analog Audio Parameters.................................................................134
Audio Decimation Filter Response .................................................135
Application Schematic ................................................................ 136
Package Outline Drawing ........................................................... 137
Datasheet Revision History........................................................ 138
FN8257 Rev. 0.00
February 9, 2012
Page
4
of 138
TW2867C
Pin Diagram
128
127
125
124
123
122
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
102
101
126
121
103
100
99
VD1[6]
98
VD1[7]
ALINKO
CLKNO1
CLKPO1
VSS
ASYNP
ADATP
ACLKP
VD1[1]
VD1[2]
VD1[4]
VD1[5]
VD1[0]
VD1[3]
VDDO
ADATM
ASYNR
ACLKR
ADATR
MPP1
MPP3
VDDO
MPP2
MPP4
RSTB
VDDI
VSS
VDDI
IRQ
VSS
VSS
CLKNO2
CLKPO2
VDDI
VD2[0]
VD2[1]
VD2[2]
VD2[3]
VSS
VD2[4]
VD2[5]
VD2[6]
VD2[7]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VDDA
AOUT
VSSA
VSSA
AINN
AIN1
AIN2
AIN3
AIN4
AIN5
VDDA
VDDV
VIN1A
VIN1B
VSSV
VSSV
VIN2A
VIN2B
VDDV
VDDV
VIN3A
VIN3B
VSSV
VSSV
VIN4A
VIN4B
VDDV
VDDVDA
NC
VSSVDA
RTERM
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
TW2867
128Pin LQFP_14x14
VDDO
XTO
XTI
VSS
CLKNO3
CLKPO3
VDDI
VD3[0]
VD3[1]
VD3[2]
VD3[3]
VSS
VD3[4]
VD3[5]
VD3[6]
VD3[7]
VDDO
CLKNO4
CLKPO4
VDDAPLL
VSSAPLL
NC
VSS
VDDVDA
SADD[1]
SADD[0]
ALINKI
VD4[7]
VD4[6]
VD4[5]
VD4[4]
VDDI
VD4[3]
VD4[2]
62
VD4[1]
63
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
59
60
61
34
35
36
37
38
39
40
33
41
58
64
VD4[0]
VDDO
TEST
SDAT
SCLK
VDDI
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
FN8257 Rev. 0.00
February 9, 2012
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