74AUP1G57
Low-power configurable multiple function gate
Rev. 8 — 23 February 2018
Product data sheet
1
General description
The 74AUP1G57 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
NOR, XNOR, inverter, and buffer. All inputs can be connected to V
CC
or GND.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging backflow current through the
device when it is powered down.
The 74AUP1G57 has Schmitt trigger inputs making it capable of transforming slowly
changing input signals into sharply defined, jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The
difference between the positive voltage V
T+
and the negative voltage V
T-
is defined as the
input hysteresis voltage V
H
.
2
Features and benefits
•
Wide supply voltage range from 0.8 V to 3.6 V
•
High noise immunity
•
ESD protection:
–
HBM JESD22-A114F exceeds 5000 V
–
MM JESD22-A115-A exceeds 200 V
–
CDM JESD22-C101E exceeds 1000 V
•
Low static power consumption; I
CC
= 0.9 μA (maximum)
•
Latch-up performance exceeds 100 mA per JESD 78 Class II
•
Inputs accept voltages up to 3.6 V
•
Low noise overshoot and undershoot < 10 % of V
CC
•
I
OFF
circuitry provides partial power-down mode operation
•
Multiple package options
•
Specified from -40 °C to +85 °C and -40 °C to +125 °C
Nexperia
Low-power configurable multiple function gate
74AUP1G57
3
Ordering information
Package
Temperature range Name
Description
plastic surface-mounted package; 6 leads
Version
SOT363
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
SC-88
XSON6
XSON6
XSON6
XSON6
X2SON6
Table 1. Ordering information
Type number
74AUP1G57GW
74AUP1G57GM
74AUP1G57GF
74AUP1G57GN
74AUP1G57GS
74AUP1G57GX
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 x 1.45 x 0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 x 1 x 0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm
extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.0 x 0.35 mm
plastic thermal extremely thin small outline package;
no leads; 6 terminals; body 1 x 0.8 x 0.35 mm
SOT1115
SOT1202
SOT1255
4
Marking
Marking code
aC
aC
aC
aC
aC
aC
[1]
Table 2. Marking
Type number
74AUP1G57GW
74AUP1G57GM
74AUP1G57GF
74AUP1G57GN
74AUP1G57GS
74AUP1G57GX
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5
Functional diagram
A
3
4
B
1
Y
C
6
001aab583
Figure 1. Logic symbol
74AUP1G57
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 8 — 23 February 2018
2 / 24
Nexperia
Low-power configurable multiple function gate
74AUP1G57
6
Pinning information
6.1 Pinning
74AUP1G57
74AUP1G57
B
GND
A
1
2
3
001aab591
B
1
6
C
6
5
4
C
V
CC
Y
GND
2
5
V
CC
A
3
4
001aab592
Y
Transparent top view
Figure 2. Pin configuration SOT363
74AUP1G57
B
GND
A
1
2
3
6
5
4
C
V
CC
Y
Figure 3. Pin configuration SOT886
74AUP1G57
B
1
GND
3
A
2
5
4
Y
C
6
V
CC
001aae058
Transparent top view
aaa-019829
Figure 4. Pin configuration SOT891, SOT1115 and
SOT1202
Transparent top view
Figure 5. Pin configuration SOT1255 (X2SON6)
6.2 Pin description
Table 3. Pin description
Symbol
B
GND
A
Y
V
CC
C
Pin
1
2
3
4
5
6
Description
data input
ground (0 V)
data input
data output
supply voltage
data input
74AUP1G57
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 8 — 23 February 2018
3 / 24
Nexperia
Low-power configurable multiple function gate
74AUP1G57
7
Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level.
Input
C
L
L
L
L
H
H
H
H
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
Output
Y
H
L
H
L
L
L
H
H
7.1 Logic configurations
Table 5. Function selection table
Logic function
2-input AND
2-input AND with both inputs inverted
2-input NAND with inverted input
2-input OR with inverted input
2-input NOR
2-input NOR with both inputs inverted
2-input XNOR
Inverter
Buffer
V
CC
B
C
B
C
Y
B
1
2
Y
3
6
5
4
Y
C
B
C
B
C
Y
B
1
2
Y
3
6
5
4
Y
C
Figure
see
Figure 6
see
Figure 9
see
Figure 7
and
Figure 8
see
Figure 7
and
Figure 8
see
Figure 9
see
Figure 6
see
Figure 10
see
Figure 11
see
Figure 12
V
CC
001aab584
001aab585
Figure 6. 2-input AND gate or 2-input NOR gate with
both inputs inverted
Figure 7. 2-input NAND gate with input B inverted or
2-input OR gate with inverted C input
74AUP1G57
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 8 — 23 February 2018
4 / 24
Nexperia
Low-power configurable multiple function gate
74AUP1G57
V
CC
V
CC
A
C
A
C
Y
1
2
Y
A
3
6
5
4
Y
C
A
C
A
C
Y
1
2
A
3
6
5
4
C
Y
Y
001aab586
001aab587
Figure 8. 2-input NAND gate with input C inverted or
2-input OR gate with inverted A input
Figure 9. 2-input NOR gate or 2-input AND gate with
both inputs inverted
V
CC
V
CC
B
C
B
Y
1
2
3
6
5
4
Y
C
A
Y
A
1
2
3
6
5
4
Y
001aab588
001aab589
Figure 10. 2-input XNOR gate
Figure 11. Inverter
V
CC
B
B
Y
1
2
3
6
5
4
Y
001aab590
Figure 12. Buffer
74AUP1G57
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 8 — 23 February 2018
5 / 24
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