DATASHEET
AUDIO CLOCK SOURCE
Description
The MK2705 provides synchronous clock generation for
audio sampling clock rates derived from an MPEG stream,
or can be used as a standalone clock source with a 27 MHz
crystal. The device uses the latest PLL technology to
provide good phase noise and long term jitter
characteristics in a small 8-pin package.
Contact IDT if you have a requirement for an input and
output frequency not included in this document.
MK2705
Features
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•
•
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Packaged in 8-pin (150 mil wide) SOIC
Clock or crystal input
Low phase noise
Low jitter
Exact (0 ppm) multiplication ratios
Independent output voltage
Support for 256 times sampling rate
Block Diagram
VDD
VDDO
S0
S1
X1/REFIN
27 MHz crystal
or clock input
Crystal
Oscillator
PLL Clock
Synthesis
and Control
Circuitry
CLK
X2
GND
Optional crystal load capacitors
IDT™
AUDIO CLOCK SOURCE
1
MK2705
REV E 051310
MK2705
AUDIO CLOCK SOURCE
CLOCK SYNTHESIZER
Application Information
Series Termination Resistor
Clock output traces should use series termination. To series
terminate a 50Ω trace (a commonly used trace impedance),
place a 33Ω resistor in series with the clock line and as close
to the clock output pin as possible. The nominal impedance
of the clock output is 20Ω
.
use very short PCB traces (and no vias) been the crystal
and device.
The value of the load capacitors can be roughly determined
by the formula C = 2(C
L
- 6) where C is the load capacitor
connected to X1 and X2, and C
L
is the specified value of the
load capacitance for the crystal. A typical crystal C
L
is 18 pF,
so C = 2(18 - 6) = 24 pF. Because these capacitors adjust
the stray capacitance of the PCB, check the output
frequency using your final layout to see if the value of C
should be changed.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the MK2705
must be isolated from system power supply noise to perform
optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. To further
guard against interfering system supply noise, the MK2705
should use one common connection to the PCB power
plane as shown in the diagram on the next page. The ferrite
bead and bulk capacitor help reduce lower frequency noise
in the supply that can lead to output clock phase modulation.
PCB Layout Recommendations
Observe the following guidelines for optimum device
performance and lowest output phase noise:
1) Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) The external crystal should be mounted next to the device
with short traces. The X1 and X2 traces should not be
routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
3) To minimize EMI and obtain the best signal integrity, the
33Ω series termination resistor should be placed close to
the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the MK2705. This includes signal traces just
underneath the device, or on layers adjacent to the ground
plane layer used by the device.
Recommended Power Supply Connection for
Optimal Device Performance
Ferrite
Bead
VDD Pin
VDD Pin
Connection to 3.3 V
Power Plane
Bulk Decoupling Capacitor
(such as 1 F Tantalum)
0.01 F Decoupling Capacitors
Both VDD pins m be connected to the sam voltage.
ust
e
Crystal Load Capacitors
If a crystal is used, the device crystal connections should
include pads for capacitors from X1 to ground and from X2
to ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally required
crystal load capacitance. To reduce possible noise pickup,
IDT™
AUDIO CLOCK SOURCE
3
MK2705
REV E 051310
MK2705
AUDIO CLOCK SOURCE
CLOCK SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2705. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
4.5 V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
-65 to +150° C
175° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.0
Typ.
Max.
+70
+3.6
Units
°
C
V
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±10%,
Ambient Temperature 0 to +70° C
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Supply Current
Short Circuit Current
Nominal Output Impedance
Input Capacitance
Internal pull-up resistor value
Symbol
VDD
VDDO
V
IH
V
IL
V
OH
V
OH
V
OL
IDD
I
OS
Z
OUT
C
IN
R
PU
Conditions
Min.
3.0
1.8
2
Typ.
Max.
3.6
VDD
0.8
Units
V
V
V
V
V
V
I
OH
= -4 mA
I
OH
= -20 mA
I
OL
= 20 mA
No Load
Each output
Input pins
VDD-0.4
2.4
0.4
24
±65
20
7
120
V
mA
mA
Ω
pF
kΩ
IDT™
AUDIO CLOCK SOURCE
4
MK2705
REV E 051310
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