74LVX4245 8-Bit Dual Supply Translating Transceiver with 3-STATE Outputs
January 1993
Revised September 2003
74LVX4245
8-Bit Dual Supply Translating Transceiver
with 3-STATE Outputs
General Description
The LVX4245 is a dual-supply, 8-bit translating transceiver
that is designed to interface between a 5V bus and a 3V
bus in a mixed 3V/5V supply environment. The Transmit/
Receive (T/R) input determines the direction of data flow.
Transmit (active-HIGH) enables data from A Ports to B
Ports; Receive (active-LOW) enables data from B Ports to
A Ports. The Output Enable input, when HIGH, disables
both A and B Ports by placing them in a high impedance
condition. The A Port interfaces with the 5V bus; the B Port
interfaces with the 3V bus.
The LVX4245 is suitable for mixed voltage applications
such as laptop computers using 3.3V CPU’s and 5V LCD
displays.
Features
s
Bidirectional interface between 5V and 3V buses
s
Control inputs compatible with TTL level
s
5V data flow at A Port and 3V data flow at B Port
s
Outputs source/sink 24 mA at 5V bus; 12 mA at 3V bus
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Implements patented EMI reduction circuitry
s
Functionally compatible with the 74 series 245
Ordering Code:
Order Number
74LVX4245WM
74LVX4245QSC
74LVX4245MTC
Package Number
M24B
MQA24
MTC24
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
T/R
A
0
–A
7
Description
Output Enable Input
Transmit/Receive Input
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
Connection Diagram
B
0
–B
7
Truth Table
Inputs
OE
L
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Outputs
T/R
L
H
X
Bus B Data to Bus A
Bus A Data to Bus B
HIGH-Z State
© 2003 Fairchild Semiconductor Corporation
DS011540
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74LVX4245
Logic Diagram
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2
74LVX4245
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CCA
, V
CCB
)
DC Input Voltage (V
I
) @ OE, T/R
DC Input/Output Voltage (V
I/O
)
@ A
n
@B
n
DC Input Diode Current (I
IN
)
@ OE, T/R
DC Output Diode Current (I
OK
)
DC Output Source or Sink Current
(I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
and Max Current @ I
CCA
@ I
CCB
Storage Temperature Range
(T
STG
)
DC Latch-Up Source or
Sink Current
−
0.5V to
+
7.0V
−
0.5V to V
CCA
+
0.5V
−
0.5V to V
CCA
+
0.5V
−
0.5V to V
CCB
+
0.5V
±
20 mA
±
50 mA
±
50 mA
±
50 mA
±
200 mA
±
100 mA
−
65
°
C to
+
150
°
C
±
300 mA
Recommended Operating
Conditions
(Note 2)
Supply Voltage
V
CCA
V
CCB
Input Voltage (V
I
) @ OE, T/R
Input/Output Voltage (V
I/O
)
@ A
n
@ B
n
Free Air Operating Temperature (T
A
)
Minimum Input Edge Rate (
∆
t/
∆
V)
V
IN
from 30% to 70% of V
CC
V
CC
@ 3.0V, 4.5V, 5.5V
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2:
Unused inputs must he held HIGH or LOW. They may not float.
4.5V to 5.5V
2.7V to 3.6V
0V to V
CCA
0V to V
CCA
0V to V
CCB
−
40
°
C to
+
85
°
C
8 ns/V
DC Electrical Characteristics
Symbol
V
IHA
V
IHB
Minimum
HIGH Level
Input Voltage
Parameter
A
n
, T/R,
OE
B
n
V
CCA
(V)
5.5
4.5
5.0
5.0
V
ILA
V
ILB
V
OHA
V
OHB
Maximum
LOW Level
Input Voltage
A
n
, T/R,
OE
B
n
5.5
4.5
5.0
5.0
Minimum HIGH Level
Output Voltage
4.5
4.5
4.5
4.5
4.5
V
OLA
V
OLB
Maximum LOW Level
Output Voltage
4.5
4.5
4.5
4.5
4.5
I
IN
Maximum Input
Leakage Current
@ OE, T/R
I
OZA
Maximum 3-STATE
Output Leakage
@ A
n
I
OZB
Maximum 3-STATE
Output Leakage
@ B
n
∆I
CC
Maximum I
CCT
/Input
@ A
n
, T/R, OE
Input @ B
n
5.5
3.6
0.35
0.5
mA
V
I
=
V
CCB
−
0.6V
5.5
3.6
1.0
1.35
1.5
mA
5.5
3.6
±0.5
±5.0
µA
5.5
3.6
±0.5
±5.0
µA
V
I
=
V
IL
, V
IH
OE
=
V
CCA
V
O
=
V
CCA
, GND
V
I
=
V
IL
, V
IH
OE
=
V
CCA
V
O
=
V
CCB
, GND
V
I
=
V
CCA
−
2.1V
5.5
3.6
±0.1
±1.0
µA
V
CCB
(V)
3.3
3.3
3.6
2.7
3.3
3.3
2.7
3.6
3.0
3.0
3.0
3.0
2.7
3.0
3.0
3.0
3.0
2.7
4.5
4.25
2.99
2.8
2.5
0.002
0.18
0.002
0.1
0.1
T
A
+25°C
Typ
2.0
2.0
2.0
2.0
0.8
0.8
0.8
0.8
4.4
3.86
2.9
2.4
2.4
0.1
0.36
0.1
0.31
0.31
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
2.0
2.0
0.8
0.8
0.8
0.8
4.4
3.76
2.9
2.4
2.4
0.1
0.44
0.1
0.4
0.4
V
V
V
V
I
OUT
= −100 µA
I
OH
= −24
mA
I
OUT
= −100 µA
I
OH
= −12
mA
I
OL
= −8
mA
I
OUT
=100 µA
I
OL
=
24 mA
I
OUT
=
100
µA
I
OL
=
12 mA
I
OL
=
8 mA
V
I
=
V
CCA
, GND
V
V
OUT
≤
0.1V or
≥
V
CC
−0.1V
V
Units
Conditions
V
OUT
≤
0.1V or
≥
V
CC
−
0.1V
3
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74LVX4245
DC Electrical Characteristics
Symbol
I
CCA
Parameter
Quiescent V
CCA
Supply Current
I
CCB
Quiescent V
CCB
Supply Current
V
OLPA
V
OLPB
V
OLVA
V
OLVB
V
IHDA
V
IHDB
V
ILDA
V
ILDB
Quiet Output Maximum
Dynamic V
OL
Quiet Output Minimum
Dynamic V
OL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
5.5
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.5
V
CCA
(V)
(Continued)
V
CCB
(V)
3.6
T
A
+25°C
Typ
8
T
A
= −40°C
to
+85°C
Guaranteed Limits
A
n
=
V
CCA
or GND
80
µA
B
n
=
V
CCB
or GND,
OE
=
GND T/R
=
GND
A
n
=
V
CCA
or GND
3.6
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
5
1.5
0.8
−1.2
−0.8
2.0
2.0
0.8
0.8
50
µA
B
n
=
V
CCB
or GND,
OE
=
GND T/R
=
V
CCA
V
V
V
V
(Note 4)(Note 5)
(Note 4)(Note 5)
(Note 4)(Note 6)
(Note 4)(Note 6)
Units
Conditions
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 4:
Worst case package.
Note 5:
Max number of outputs defined as (n). Data inputs are driven 0V to V
CC
level; one output at GND.
Note 6:
Max number of Data Inputs (n) switching. (n−1) inputs switching 0V to V
CC
level. Input-under-test switching:
V
CC
level to threshold (V
IHD
), OV to threshold (V
ILD
), f
=
1 MHz.
AC Electrical Characteristics
T
A
= +25°C
C
L
=
50 pF
Symbol
Parameters
V
CCA
=
5V (Note 7)
V
CCB
=
3.3V (Note 8)
Min
t
PHL
t
PLH
t
PHL
t
PLH
t
PZL
t
PZH
t
PZL
t
PZH
t
PHZ
t
PLZ
t
PHZ
t
PLZ
t
OSHL
t
OSLH
Propagation Delay
A to B
Propagation Delay
B to A
Output Enable Time
OE to B
Output Enable Time
OE to A
Output Disable Time
OE to B
Output Disable Time
OE to A
Output to Output
Skew (Note 9)
Data to Output
Note 7:
Voltage Range 5.0V is 5.0V
±
0.5V.
Note 8:
Voltage Range 3.3V is 3.3V
±
0.3V.
Note 9:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
T
A
= −40°C
to
+85°C
T
A
= −40°C
to
+85°C
C
L
=
50 pF
V
CCA
=
5V (Note 7)
V
CCB
=
3.3V (Note 8)
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
9.0
9.0
9.0
9.0
10.5
10.5
9.5
9.5
10.0
7.0
7.5
7.0
1.5
C
L
=
50 pF
V
CCA
=
5V (Note 7)
V
CCB
=
2.7V
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
10.0
10.0
10.0
10.0
11.5
11.5
10.0
10.0
10.0
7.5
7.5
7.5
1.5
ns
ns
ns
ns
ns
ns
Units
Typ
5.1
5.3
5.4
5.5
6.5
6.7
5.2
5.8
6.0
3.3
3.9
2.9
1.0
Max
8.5
8.5
8.5
8.5
10.0
10.0
9.0
9.0
9.5
6.5
7.0
6.5
1.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
ns
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4
74LVX4245
Capacitance
Symbol
C
IN
C
I/O
C
PD
Input/Output
Capacitance
Power Dissipation
Capacitance (Note 10)
Note 10:
C
PD
is measured at 10 MHz
Parameter
Input Capacitance
Typ
4.5
15
B→A
A→B
55
40
Units
pF
pF
pF
pF
Conditions
V
CC
=
Open
V
CCA
=
5.0V
V
CCB
=
3.3V
V
CCA
=
5.0V
V
CCB
=
3.3V
8-Bit Dual Supply Translating Transceiver
The LVX4245 is a dual supply device capable of bidirec-
tional signal translation. This level shifting ability provides
an efficient interface between low voltage CPU local bus
with memory and a standard bus defined by 5V I/O levels.
The device control inputs can be controlled by either the
low voltage CPU and core logic or a bus arbitrator with 5V
I/O levels.
Manufactured on a sub-micron CMOS process, the
LVX4245 is ideal for mixed voltage applications such as
notebook computers using 3.3V CPU’s and 5V peripheral
devices.
Power Up Considerations
To insure the system does not experience unnecessary I
CC
current draw, bus contention, or oscillations during power
up, the following guidelines should be adhered to (refer to
Table 1):
• Power up the control side of the device first. This is the
V
CCA
.
• OE should ramp with or ahead of V
CCA
. This will help
guard against bus contention.
• The Transmit/Receive control pin (T/R) should ramp with
or ahead of V
CCA
, this will ensure that the A Port data
pins are configured as inputs. With V
CCA
receiving
power first, the A I/O Port should be configured as inputs
to help guard against bus contention and oscillations.
• A side data inputs should be driven to a valid logic level.
This will prevent excessive current draw.
The above steps will ensure that no bus contention or oscil-
lations, and therefore no excessive current draw occurs
during the power up cycling of these devices. These steps
will help prevent possible damage to the translator devices
and potential damage to other system components.
TABLE 1. Low Voltage Translator Power Up Sequencing Table
Device Type
74LVX4245
V
CCA
5V
(power up 1st)
V
CCB
3V
(power up 2nd)
T/R
ramp
with V
CCA
OE
ramp
with V
CCA
A Side
I/O
logic
0V or V
CCA
B Side
I/O
outputs
Floatable Pin
Allowed
No
Please reference Application Note AN-5001 for more detailed information on using Fairchild’s LVX Low Voltage Dual
Supply CMOS Translating Transceivers.
5
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