IS65LV256AL
IS62LV256AL
32K x 8 LOW VOLTAGE
CMOS STATIC RAM
FEATURES
• High-speed access time: 20, 45 ns
• Automatic power-down when chip is deselected
• CMOS low power operation
— 17 µW (typical) CMOS standby
— 50 mW (typical) operating
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three-state outputs
• Industrial and Automotive temperatures available
• Lead-free available
JULY 2015
DESCRIPTION
The
ISSI
IS62/65LV256AL is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using
ISSI
's
high-performance CMOS technology. This highly reliable
process coupled with innovative circuit design techniques,
yields access times as fast as 15 ns maximum.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation is reduced to
150 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active
LOW Chip Enable (CE). The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS62/65LV256AL is available in the JEDEC standard
28-pin SOJ, 28-pin SOP, and the 28-pin TSOP (Type I)
package.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
DECODER
32K x 8
MEMORY ARRAY
VDD
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. D
07/20/2015
1
IS65LV256AL
IS62LV256AL
PIN CONFIGURATION
28-Pin SOJ/ 28-pin SOP
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIN CONFIGURATION
28-Pin TSOP
VDD
28
27
26
25
24
23
22
21
20
19
18
17
16
15
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
OE
A11
A9
A8
A13
WE
VDD
A14
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
PIN DESCRIPTIONS
A0-A14 Address Inputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7 Input/Output
V
dd
Power
GND
Ground
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE
X
H
H
L
CE
H
L
L
L
OE
X
H
L
X
I/O Operation
High-Z
High-Z
d
out
d
In
V
DD
Current
I
sb
1
, I
sb
2
I
cc
1
, I
cc
2
I
cc
1
, I
cc
2
I
cc
1
, I
cc
2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
term
t
bIas
t
stg
P
t
I
out
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +4.6
–55 to +125
–65 to +150
0.5
20
Unit
V
°C
°C
W
mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nent damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. D
07/20/2015
IS65LV256AL
IS62LV256AL
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE Access Time
OE Access Time
OE to Low-Z Output
OE to High-Z Output
CE to Low-Z Output
CE to High-Z Output
CE to Power-Up
CE to Power-Down
-20 ns
Min. Max.
20
—
2
—
—
0
—
3
—
0
—
—
20
—
20
10
—
9
—
9
—
18
-45 ns
Min. Max.
45
—
2
—
—
0
0
3
0
0
—
—
45
—
45
25
—
20
—
20
—
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
rc
t
aa
t
oha
t
ace
t
doe
t
lzoe
(2)
t
hzoe
(2)
t
lzce
(2)
t
hzce
(2)
t
Pu
(3)
t
Pd
(3)
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
635
Ω
3.3V
OUTPUT
30 pF
Including
jig and
scope
702
Ω
3.3V
OUTPUT
5 pF
Including
jig and
scope
702
Ω
635
Ω
Figure 1.
Figure 2.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. D
07/20/2015
5
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