CY2544/CY2548, CY2546
Quad PLL Programmable Clock Generator
with Spread Spectrum
Quad PLL Programmable Clock Generator
Features
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Up to nine clock outputs with programmable drive strength
Glitch free outputs while frequency switching
24-pin QFN package
Commercial and Industrial temperature ranges
Four fully integrated phase locked loops (PLLs)
Input frequency range
❐
External crystal: 8 to 48 MHz for CY2544 and CY2546
❐
External reference: 8 to 166 MHz clock
Reference clock input voltage range
❐
2.5V, 3.0V, and 3.3V for CY2548
❐
1.8V for CY2544 and CY2546
Wide operating output frequency range
❐
3 to 166 MHz
Programmable spread spectrum with center and down
spread option and Lexmark and Linear modulation profiles
VDD supply voltage options:
❐
2.5V, 3.0V, and 3.3V for CY2544 and CY2548
❐
1.8V for CY2546
Selectable output clock voltages:
❐
2.5V, 3.0V, and 3.3V for CY2544 and CY2548
❐
1.8V for CY2546
Frequency select feature with option to select eight different
frequencies over nine clock outputs
Power down, output enable, and SS ON/OFF controls
Low jitter, high accuracy outputs
Ability to synthesize nonstandard frequencies with
Fractional-N capability
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Benefits
■
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Multiple high performance PLLs allow synthesis of unrelated
frequencies
Nonvolatile programming for personalization of PLL
frequencies, spread spectrum characteristics, drive strength,
crystal load capacitance, and output frequencies
Application specific programmable EMI reduction using
spread spectrum for clocks
Programmable PLLs for system frequency margin tests
Meets critical timing requirements in complex system
designs
Suitability for PC, consumer, portable, and networking
applications
Capable of Zero PPM frequency synthesis error
Uninterrupted system operation during clock frequency
switch
Application compatibility in standard and low power systems
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Logic Block Diagram
CLKIN
Crossbar
Switch
OSC
PLL1
Output
Dividers
and
Bank
2
CLK1
Bank
1
XIN/
EXCLKIN
XOUT
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
FS 0
FS 1
FS 2
MUX
and
Control
Logic
PLL2
Drive
Strength
Control
Bank
PLL3
(SS)
3
CLK8
CLK9
PLL4
(SS)
SSON
PD#/OE
Cypress Semiconductor Corporation
Document #: 001-12563 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 21, 2010
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CY2544/CY2548, CY2546
Contents
General Description ......................................................... 5
Four Configurable PLLs .............................................. 5
Input Reference Clocks ............................................... 5
Multiple Power Supplies .............................................. 5
Output Bank Settings .................................................. 5
Output Source Selection ............................................. 5
Spread Spectrum Control ............................................ 5
Frequency Select ........................................................ 6
Glitch-Free Frequency Switch ..................................... 6
PD#/OE Mode ............................................................. 6
Output Drive Strength .................................................. 6
Generic Configuration and Custom Frequency ........... 6
Absolute Maximum Conditions ....................................... 7
Recommended Operating Conditions ............................ 7
DC Electrical Specifications ............................................ 8
AC Electrical Specifications ............................................ 9
Recommended Crystal Specification for SMD Package 9
Test and Measurement Setup ........................................ 10
Voltage and Timing Definitions ..................................... 10
Recommended Crystal Specification for
Thru-Hole Package ......................................................... 10
Ordering Information ...................................................... 11
Possible Configurations ............................................. 11
Ordering Code Definition ........................................... 12
Package Drawing and Dimensions ............................... 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC Solutions ......................................................... 16
Document #: 001-12563 Rev. *G
Page 2 of 16
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CY2544/CY2548, CY2546
Table 1. Device Selection Guide
Device
CY2544
CY2546
CY2548
Crystal Input
Yes
Yes
No
EXCKLKIN Input
1.8 V LVCMOS
1.8 V LVCMOS
CLKIN Input
1.8 V LVCMOS
VDD
1.8 V
VDD_CLK_BX
1.8 V
2.5 V, 3.0 V, 3.3 V LVCMOS 2.5 V, 3.0 V, 3.3 V 2.5 V, 3.0 V, 3.3 V
2.5 V, 3.0 V, 3.3 V LVCMOS 2.5 V, 3.0 V, 3.3 V LVCMOS 2.5 V, 3.0 V, 3.3 V 2.5 V, 3.0 V, 3.3 V
Figure 1. Pin Diagram – CY2544/CY2548 24 LD QFN
XIN/
EXCLKIN
EXCLKIN
CLKIN
CLKIN
XOUT
CLK9
20
CLK9
24
23
22
21
20
19
24
23
22
21
GND
CLK1
VDD_CLK_B1
PD#OE
NC
CLK2
1
18
GND
CLK8
VDD_CLK_B3
CLK7/SSON
VDD_CLK_B2
CLK6
GND
19
GND
DNU
VDD
VDD
GND
CLK1
VDD_CLK_B1
PD#OE
NC
CLK2
1
18
GND
CLK8
VDD_CLK_B3
CLK7/SSON
VDD_CLK_B2
CLK6
2
17
2
17
3
CY2544
24LD QFN
16
3
CY2548
24LD QFN
16
4
15
4
15
5
14
5
14
6
13
6
13
7
8
9
10
11
12
7
8
9
10
11
12
OE/FS1
CLK3/FS0
CLK4/FS2
CLK3/FS0
OE/FS1
CLK4/FS2
CLK5
Table 2. Pin Definition – CY2544/CY2548 (VDD = 2.5 V, 3.0 V or 3.3 V Supply)
Pin Number
1
GND
Name
Power
IO
Power supply ground
Output
Power
Input
NC
Output
Power
Description
Programmable clock output.
Output voltage depends on
VDD_CLK_B1
voltage
Power supply for bank1, (CLK1, CLK2, CLK3) Outputs:
2.5 V/3.0 V/3.3 V
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK1
VDD_CLK_B1
PD#/OE
NC
CLK2
GND
Multifunction programmable pin.
Output enable or power-down mode
No Connect
Programmable Clock Output.
Output voltage depends on
VDD_CLK_B1
voltage
Power supply ground
Multifunction programmable pin.
Programmable clock
output clock or
frequency select pin. Output voltage of
CLK3
depends on
VDD_CLK_B1
voltage
CLK3/FS0
OE/FS1
CLK4/FS2
CLK5
GND
CLK6
VDD_CLK_B2
CLK7/SSON
VDD_CLK_B3
Output/input
Input
Output/input
Output
Power
Output
Power
Output/input
Power
Multifunction programmable pin.
Output enable or frequency select pin
Multifunction programmable pin.
Programmable clock output or frequency
select input pin.
Output voltage of
CLK4
depends on
VDD_CLK_B2
voltage
Programmable clock output.
Output voltage depends on
VDD_CLK_B2
voltage
Power supply ground
Programmable clock
output.
Output voltage depends on
VDD_CLK_B2
voltage
Power supply for bank2, (CLK4, CLK5, CLK6) Outputs.
2.5 V/3.0 V/3.3 V
Multifunction programmable pin.
Programmable clock output or
spread
spectrum ON/OFF control input pin. Output voltage of
CLK7
depends on Bank3
voltage
Power supply for bank3, (CLK7, CLK8, CLK9) Outputs.
2.5 V/3.0 V/3.3 V
Document #: 001-12563 Rev. *G
CLK5
GND
GND
GND
GND
Page 3 of 16
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CY2544/CY2548, CY2546
Table 2. Pin Definition – CY2544/CY2548 (VDD = 2.5 V, 3.0 V or 3.3 V Supply)
(continued)
Pin Number
17
18
19
20
21
22
23
24
CLK8
GND
GND
CLK9
CLKIN
VDD
XOUT
DNU
XIN/EXCLKIN
EXCLKIN
Name
Power
Power
IO
Output
Description
Programmable output clock.
Output voltage depends on Bank3 voltage
Power supply ground
Power supply ground
Programmable clock
output.
Output voltage depends on
VDD_CLK_B3
voltage
2.5 V/3.0 V/3.3 V
reference clock input.
The signal level of CLKIN input must
track
VDD power supply on pin 22.
Output
Input
Power
Output
Output
Input
Input
Power supply.
2.5 V/3.0 V/3.3 V
Crystal output
for CY2544
Do not use this pin
for CY2548
Crystal input or 1.8 V external clock input for CY2544
2.5 V/3.0 V/3.3 V
external clock input for CY2548
Figure 2. Pin Diagram – CY2546 24 LD QFN
XIN/
EXCLKIN
CLKIN
XOUT
CLK9
20
VDD
24
23
22
21
GND
CLK1
VDD_CLK_B1
PD#OE
VDD
CLK2
GND
19
1
18
GND
CLK8
VDD_CLK_B3
CLK7/SSON
VDD_CLK_B2
CLK6
2
17
3
CY2546
24LD QFN
16
4
15
5
14
6
13
7
8
9
10
11
12
CLK3/FS0
OE/FS1
Table 3. Pin Definition – CY2546 (VDD = 1.8 V Supply)
Pin Number
1
GND
Name
Power
IO
Output
Power
Input
Power
Output
Power
Output/Input
CLK4/FS2
CLK5
GND
GND
Description
Power supply ground
Programmable clock
output.
Output voltage depends on VDD_CLK_B1
voltage
Power supply for bank1, (CLK1, CLK2, CLK3) Outputs.
1.8V
Multifunction programmable pin.
Output enable or power down mode
Power supply.
1.8 V
Programmable clock
output.
Output voltage depends on VDD_CLK_B1
voltage
Power supply ground
Multifunction programmable pin.
Programmable clock
output or frequency
select input pin. Output voltage of
CLK3
depends on VDD_CLK_B1 voltage
Multifunction programmable pin.
Output enable or frequency select pin
Multifunction programmable pin.
Programmable clock output or frequency
select input pin.
Output voltage of
CLK4
depends on VDD_CLK_B2 voltage
Programmable clock
output.
Output voltage depends on VDD_CLK_B2
voltage
Page 4 of 16
2
3
4
5
6
7
8
9
10
11
CLK1
VDD_CLK_B1
PD#/OE
VDD
CLK2
GND
CLK3/FS0
OE/FS1
CLK4/FS2
CLK5
Input
Output/Input
Output
Document #: 001-12563 Rev. *G
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CY2544/CY2548, CY2546
Table 3. Pin Definition – CY2546 (VDD = 1.8 V Supply)
(continued)
Pin Number
Name
12
GND
13
CLK6
14
15
16
17
18
19
20
VDD_CLK_B2
CLK7/SSON
VDD_CLK_B3
CLK8
GND
GND
CLK9
IO
Power
Output
Power
Output/input
Power
Output
Power
Power
Output
Description
Power supply ground
Programmable clock
output.
Output voltage depends on VDD_CLK_B2
voltage
Power supply for bank2, (CLK4, CLK5, CLK6) Outputs.
1.8 V
Multifunction programmable pin.
Programmable clock output or
spread
spectrum ON/OFF control input pin. Output voltage of
CLK7
depends on
VDD_CLK_B3 voltage
Power supply for bank3, (CLK7, CLK8, CLK9) Outputs.
1.8 V
Programmable clock
output.
Output voltage depends on VDD_CLK_B3
voltage
Power supply ground
Power supply ground
Programmable clock
output.
Output voltage depends on VDD_CLK_B3
voltage
External 1.8 V low voltage reference clock input
Power supply.
1.8 V
Crystal output
Crystal input or 1.8 V external clock input
21
22
23
24
CLKIN
VDD
XOUT
XIN/EXCLKIN
Input
Power
Output
Input
General Description
Four Configurable PLLs
The CY2544, CY2548 and CY2546 have four programmable
PLLs that can be used to generate output frequencies ranging
from 3 to 166 MHz. The advantage of having four PLLs is that a
single device generates up to four independent frequencies from
a single crystal.
Output Bank Settings
There are nine clock outputs grouped in three output driver
banks. The Bank 1, Bank 2, and Bank 3 correspond to (CLK1,
CLK2, CLK3), (CLK4, CLK5, CLK6), and (CLK7, CLK8, CLK9)
respectively. Separate power supplies are used for each of these
banks and they can be any of 2.5 V, 3.0 V, or 3.3 V for
CY2544/CY2548 and 1.8 V for CY2546 giving user multiple
choice of output clock voltage levels.
Input Reference Clocks
The input to the CY2544, CY2548 and CY2546 can be either a
crystal or a clock signal. The input frequency range for crystal
(XIN) is 8 MHz to 48 MHz and that for external reference clock
(EXCLKIN) is 8 MHz to 166 MHz. The voltage range for the
reference clock input of CY2548 is 2.5 V/3.0 V/3.3 V while that
for CY2544 and CY2546 is 1.8 V. This gives user an option for
this device to be compatible for different input clock voltage
levels in the system.
There is provision for a secondary reference clock input, CLKIN
with applied frequency range of 8 MHz to 166 MHz. When CLKIN
signal at pin 21 is used as a reference input to the PLL, a valid
signal at EXCLKIN (as specified in the AC and DC Electrical
Specification table) must be present for the devices to operate
properly.
Output Source Selection
These devices have programmable input sources for each of its
nine clock outputs (CLK1–9). There are six available clock
sources for these outputs. These clock sources are:
XIN/EXCLKIN, CLKIN, PLL1, PLL2, PLL3, or PLL4. Output clock
source selection is done using four out of six crossbar switch.
Thus, any one of these six available clock sources can be
arbitrarily selected for the clock outputs. This gives user a
flexibility to have up to four independent clock outputs.
Spread Spectrum Control
Two of the four PLLs (PLL3 and PLL4) have spread spectrum
capability for EMI reduction in the system. The device uses a
Cypress proprietary PLL and spread spectrum clock (SSC)
technology to synthesize and modulate the frequency of the PLL.
The spread spectrum feature can be turned on or off using a
multifunction control pin (CLK7/SSON). It can be programmed to
either center spread range from ±0.125% to ±2.50% or down
spread range from –0.25% to –5.0% with Lexmark or Linear
profile.
Multiple Power Supplies
These devices are designed to operate at internal supply voltage
of 1.8 V. In the case of the high voltage part (CY2544/CY2548),
an internal regulator is used to generate 1.8 V from the 2.5 V/3.0
V/3.3 V VDD supply voltage at pin 22. For the low voltage part
(CY2546), this internal regulator is bypassed and 1.8 V at VDD
pin 22 is directly used.
Document #: 001-12563 Rev. *G
Page 5 of 16
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