Philips Semiconductors
Product specification
Digital video encoder
CONTENTS
1
2
3
4
5
6
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
7.21
7.22
7.23
7.24
7.25
FEATURES
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Reset conditions
Input formatter
RGB LUT
Cursor insertion
RGB Y-C
B
-C
R
matrix
Horizontal scaler
Vertical scaler and anti-flicker filter
FIFO
Border generator
Oscillator and Discrete Time Oscillator (DTO)
Low-pass Clock Generation Circuit (CGC)
Encoder
RGB processor
Triple DAC
HD data path
Timing generator
Pattern generator for HD sync pulses
I
2
C-bus interface
Power-down modes
Programming the SAA7104H; SAA7105H
Input levels and formats
Bit allocation map
I
2
C-bus format
Slave receiver
Slave transmitter
8
8.1
8.2
9
10
11
11.1
12
12.1
12.2
12.3
13
14
14.1
14.2
14.3
14.4
14.5
15
16
17
18
SAA7104H; SAA7105H
BOUNDARY SCAN TEST
Initialization of boundary scan circuit
Device identification codes
LIMITING VALUES
THERMAL CHARACTERISTICS
CHARACTERISTICS
Teletext timing
APPLICATION INFORMATION
Reconstruction filter
Analog output voltages
Suggestions for a board layout
PACKAGE OUTLINE
SOLDERING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
DATA SHEET STATUS
DEFINITIONS
DISCLAIMERS
PURCHASE OF PHILIPS I
2
C COMPONENTS
2004 Mar 04
2
Philips Semiconductors
Product specification
Digital video encoder
1
FEATURES
SAA7104H; SAA7105H
•
Digital PAL/NTSC encoder with integrated high quality
scaler and anti-flicker filter for TV output from a PC
•
Supports Intel® Digital Video Out (DVO) low voltage
interfacing to graphics controller
•
27 MHz crystal-stable subcarrier generation
•
Maximum graphics pixel clock 85 MHz at double edged
clocking, synthesized on-chip or from external source
•
Programmable assignment of clock edge to bytes (in
double edged mode)
•
Synthesizable pixel clock (PIXCLK) with minimized
output jitter, can be used as reference clock for the VGC,
as well)
•
PIXCLK output and bi-phase PIXCLK input (VGC clock
loop-through possible)
•
Hot-plug detection through dedicated interrupt pin
•
Supported VGA resolutions for PAL or NTSC legacy
video output up to 1280
×
1024 graphics data at
60 or 50 Hz frame rate
•
Supported VGA resolutions for HDTV output up to
1920
×
1080 interlaced graphics data at 60 or 50 Hz
frame rate
•
Three Digital-to-Analog Converters (DACs) for CVBS
(BLUE, C
B
), VBS (GREEN, CVBS) and C (RED, C
R
) at
27 MHz sample rate (signals in parenthesis are
optionally), all at 10-bit resolution
•
Non-interlaced C
B
-Y-C
R
or RGB input at maximum
4 : 4 : 4 sampling
•
Downscaling and upscaling from 50 to 400%
•
Optional interlaced C
B
-Y-C
R
input of Digital Versatile
Disk (DVD) signals
•
Optional non-interlaced RGB output to drive second
VGA monitor (bypass mode, maximum 85 MHz)
•
3
×
256 bytes RGB Look-Up Table (LUT)
•
Support for hardware cursor
•
HDTV up to 1920
×
1080 interlaced and 1280
×
720
progressive, including 3-level sync pulses
•
Programmable border colour of underscan area
•
Programmable 5 line anti-flicker filter
•
On-chip 27 MHz crystal oscillator (3rd-harmonic or
fundamental 27 MHz crystal)
•
Fast I
2
C-bus control port (400 kHz)
•
Encoder can be master or slave
•
Adjustable output levels for the DACs
•
Programmable horizontal and vertical input
synchronization phase
•
Programmable horizontal sync output phase
•
Internal Colour Bar Generator (CBG)
•
Optional support of various Vertical Blanking Interval
(VBI) data insertion
•
Macrovision™
(1)
Pay-per-View copy protection system
rev. 7.01, rev. 6.1 and rev. 1.03 (525p) as option; this
applies to the SAA7104H only. The device is protected
by USA patent numbers 4631603, 4577216 and
4819098 and other intellectual property rights. Use of
the Macrovision anti-copy process in the device is
licensed for non-commercial home use only. Reverse
engineering or disassembly is prohibited. Please
contact your nearest Philips Semiconductors sales
office for more information.
•
Optional cross-colour reduction for PAL and NTSC
CVBS outputs
•
Power-save modes
•
Joint Test Action Group (JTAG) boundary scan test
•
Monolithic CMOS 3.3 V device, 5 V tolerant I/Os
•
QFP64 package.
(1) Macrovision™ is a trademark of the Macrovision Corporation.
2004 Mar 04
3
Philips Semiconductors
Product specification
Digital video encoder
2
GENERAL DESCRIPTION
SAA7104H; SAA7105H
When the scaler/interlacer is bypassed, a second VGA
monitor can be connected to the RGB outputs and
separate H and V-syncs as well, thereby serving as an
auxiliary monitor at maximum 1280
×
1024
resolution/60 Hz (PIXCLK < 85 MHz). Alternatively this
port can provide Y, P
B
and P
R
signals for HDTV monitors.
The device includes a sync/clock generator and on-chip
DACs.
All inputs intended to interface to the host graphics
controller are designed for low-voltage signals between
down to 1.1 V and up to 3.6 V.
The SAA7104H; SAA7105H is an advanced
next-generation video encoder which converts PC
graphics data at maximum 1280
×
1024 resolution
(optionally 1920
×
1080 interlaced) to PAL (50 Hz) or
NTSC (60 Hz) video signals. A programmable scaler and
anti-flicker filter (maximum 5 lines) ensures properly sized
and flicker-free TV display as CVBS or S-video output.
Alternatively, the three Digital-to-Analog Converters
(DACs) can output RGB signals together with a TTL
composite sync to feed SCART connectors.
3
QUICK REFERENCE DATA
SYMBOL
V
DDA
V
DDD
I
DDA
I
DDD
V
i
V
o(p-p)
R
L
ILE
lf(DAC)
DLE
lf(DAC)
T
amb
4
PARAMETER
analog supply voltage
digital supply voltage
analog supply current
digital supply current
input signal voltage levels
MIN.
3.15
3.15
1
1
−
−
−
−
0
TYP.
3.3
3.3
110
175
1.23
37.5
−
−
−
MAX.
3.45
3.45
115
200
−
−
±3
±1
70
V
V
UNIT
mA
mA
V
Ω
LSB
LSB
°C
TTL compatible
analog CVBS output signal voltage for a 100/100
colour bar at 75/2
Ω
load (peak-to-peak value)
load resistance
low frequency integral linearity error of DACs
low frequency differential linearity error of DACs
ambient temperature
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
plastic quad flat package; 64 leads (lead length 1.6 mm);
body 14
×
14
×
2.7 mm
VERSION
SOT393-1
SAA7104H
SAA7105H
QFP64
2004 Mar 04
4
NXP MCU
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