ISP1705
ULPI Hi-Speed USB transceiver
Rev. 01 — 13 June 2008
Product data sheet
1. General description
The ISP1705 is a UTMI+ Low Pin Interface (ULPI) Hi-Speed Universal Serial Bus (USB)
transceiver that is fully compliant with
Universal Serial Bus Specification Rev. 2.0,
On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3
and
UTMI+ Low Pin
Interface (ULPI) Specification Rev. 1.1.
The ISP1705 can transmit and receive USB data at high speed (480 Mbit/s), full speed
(12 Mbit/s) and low speed (1.5 Mbit/s), and provides a pin-optimized, physical layer
front-end attachment to the USB host, peripheral or OTG controller with Single Data Rate
(SDR) or Dual Data Rate (DDR) ULPI link. The ISP1705 can transparently transmit and
receive UART signaling.
It is ideal for use in portable electronic devices, such as mobile phones, digital still
cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio
players. It allows USB Application-Specific Integrated Circuits (ASICs), Programmable
Logic Devices (PLDs) or any system chip set to interface with the physical layer of the
USB through an 8-pin (DDR) or 12-pin (SDR) interface.
The ISP1705 can interface to devices with digital I/O voltages in the range of 3.0 V to
3.6 V.
The ISP1705 is available in HVQFN36 and TFBGA36 packages.
2. Features
I
Fully complies with:
N
USB:
Universal Serial Bus Specification Rev. 2.0
N
OTG:
On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3
N
ULPI:
UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1
I
Interfaces to USB host, peripheral or OTG cores; optimized for portable devices or
system ASICs with built-in ULPI link
I
Complete Hi-Speed USB physical front-end solution that supports high speed
(480 Mbit/s), full speed (12 Mbit/s) and low speed (1.5 Mbit/s)
N
Integrated 45
Ω ±
10 % high-speed termination resistors, 1.5 kΩ
±
5 % full-speed
device pull-up resistor, and 15 kΩ
±
5 % host termination resistors
N
Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive
N
USB clock and data recovery to receive USB data up to
±500
ppm
N
Insertion of stuff bits during transmit and discarding of stuff bits during receive
N
Non-Return-to-Zero Inverted (NRZI) encoding and decoding
N
Supports bus reset, suspend, resume and high-speed detection handshake (chirp)
NXP Semiconductors
ISP1705
ULPI Hi-Speed USB transceiver
I
Complete USB OTG physical front-end that supports Host Negotiation Protocol (HNP)
and Session Request Protocol (SRP)
N
Supports external charge pump or external V
BUS
power switch
N
Complete control over USB termination resistors
N
Data line and V
BUS
pulsing session request methods
N
Integrated V
BUS
voltage comparators
N
Integrated cable (ID) detector
I
Flexible system integration and very low power consumption, optimized for portable
devices
N
3.0 V to 4.5 V supply voltage input range
N
Internal voltage regulator supplies 2.7 V or 3.3 V and 1.8 V
N
Supports interfacing I/O voltage of 3.0 V to 3.6 V; separate I/O voltage supply pins
minimize crosstalk
N
Power down internal regulators in Power-down mode when V
CC(I/O)
is not present
or when the chip is not selected
N
Typical operating current of 13 mA to 32 mA, depending on the USB speed and
bus utilization
N
Typical current consumption I
CC
is 70
µA
in suspend mode and 0.5
µA
in
Power-down mode
N
3-state ULPI interface by the CHIP_SEL or CHIP_SEL_N pin, allowing bus reuse
by other applications
I
Highly optimized ULPI compliant
N
60 MHz, 8-pin or 12-pin interface between the core and the transceiver, including a
4-bit DDR bus or an 8-bit SDR bus
N
DDR or SDR interface selectable by pin
N
Supports 60 MHz output clock configuration
N
Integrated Phase-Locked Loop (PLL) supporting input clock frequencies of
13 MHz, 19.2 MHz, 24 MHz or 26 MHz
N
Crystal or clock frequency selectable by pin
N
Fully programmable ULPI-compliant register set
N
3-pin or 6-pin full-speed or low-speed serial mode
N
Internal Power-On Reset (POR) circuit
I
UART interface:
N
Supports transparent UART signaling on DP and DM pins for the UART accessory
application
N
2.7 V UART signaling on DP and DM pins
N
Entering UART mode by register setting
N
Exiting UART mode by asserting STP or by toggling the CHIP_SEL or
CHIP_SEL_N pin
I
Full industrial grade operating temperature range from
−40 °C
to +85
°C
I
ESD compliance:
N
JESD22-A114D 2 kV contact Human Body Model (HBM)
N
JESD22-A115-A 200 V Machine Model (MM)
N
JESD22-C101-C 500 V Charged Device Model (CDM)
N
IEC 61000-4-2 8 kV contact on the DP and DM pins
ISP1705_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 June 2008
2 of 89
NXP Semiconductors
ISP1705
ULPI Hi-Speed USB transceiver
I
Available in small HVQFN36 and TFBGA36 Restriction of Hazardous Substances
(RoHS) compliant, halogen-free and lead-free packages
3. Applications
I
I
I
I
Digital still camera
Digital TV
Digital Video Disc (DVD) recorder
External storage device, for example:
N
Magneto-Optical (MO) drive
N
Optical drive (CD-ROM, CD-RW, CD-DVD)
N
Zip drive
Mobile phone
MP3 player
PDA
Printer
Scanner
Set-Top Box (STB)
Video camera
I
I
I
I
I
I
I
4. Ordering information
Table 1.
Ordering information
Package
Name
ISP1705HN
ISP1705AET
HVQFN36
TFBGA36
Description
Version
plastic thermal enhanced very thin quad flat package; SOT818-1
no leads; 36 terminals; body 5
×
5
×
0.85 mm
plastic thin fine-pitch ball grid array package; 36 balls; SOT912-1
body 3.5
×
3.5
×
0.8 mm
Type number
5. Marking
Table 2.
Marking codes
Marking code
[1]
1705
705A
Type number
ISP1705HN
ISP1705AET
[1]
The package marking is the first line of text on the IC package and can be used for IC identification.
ISP1705_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 June 2008
3 of 89
NXP Semiconductors
ISP1705
ULPI Hi-Speed USB transceiver
6. Block diagram
CLOCK
8
29
1, 2, 24,
25, 27, 28,
30, 36
19
22
23
REGISTER
MAP
USB DATA
DESERIALIZER
TERMINATION
RESISTORS
5
DM
ULPI
INTERFACE
CONTROLLER
USB DATA
SERIALIZER
6
HI-SPEED
USB ATX
DP
ULPI
INTERFACE
DATA
[7:0]
DIR
STP
NXT
DATA0
DATA1
CFG0
7
DDR OR SDR
SELECTION
UART
BUFFER
OTG MODULE
CHIP_SEL_N
CHIP_SEL
CFG1
CFG2
34
35
31
32
CLOCK
FREQUENCY
SELECTION
ISP1705
ID
DETECTOR
9
ID
V
BUS
COMPARATORS
13
SRP CHARGE
AND DISCHARGE
RESISTORS
V
BUS
GLOBAL
CLOCKS
XTAL1
XTAL2
V
CC(I/O)
18
12
8
16
17
3, 21, 26, 33
PLL
CRYSTAL
OSCILLATOR
interface voltage
internal power
PORT
POWER
CONTROL
POWER-ON
RESET
POR
BAND GAP
REFERENCE
VOLTAGE
14
10
20
PSW_N
FAULT
RESET_N
REG1V8
REG3V3
V
CC
V
REF
VOLTAGE
REGULATOR
15
11
4
RREF
004aaa994
GND
n.c.
This figure shows the HVQFN pinout. For the TFBGA ballout, see
Table 3.
Fig 1.
Block diagram
ISP1705_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 June 2008
4 of 89
NXP Semiconductors
ISP1705
ULPI Hi-Speed USB transceiver
7. Pinning information
7.1 Pinning
34 CHIP_SEL_N
35 CHIP_SEL
33 V
CC(I/O)
29 CLOCK
36 DATA2
30 DATA3
terminal 1
index area
DATA1
DATA0
V
CC(I/O)
RREF
DM
DP
CFG0
V
CC
ID
28 DATA4
27 DATA5
26 V
CC(I/O)
25 DATA6
24 DATA7
23 NXT
22 STP
21 V
CC(I/O)
20 RESET_N
19 DIR
REG1V8 18
32 CFG2
PSW_N 14
1
2
3
4
5
6
7
8
9
FAULT 10
n.c. 11
REG3V3 12
V
BUS
13
GND 15
XTAL1 16
XTAL2 17
ISP1705HN
31 CFG1
004aaa995
Transparent top view
Fig 2.
Pin configuration HVQFN36
ball A1
index area
1
A
B
C
D
E
F
ISP1705AET
2
3
4
5
6
004aab094
Transparent top view
Fig 3.
Pin configuration TFBGA36
ISP1705_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 June 2008
5 of 89
无线连接
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
