GS8182S18D-200/167
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• DLL circuitry for wide output data valid window and future
frequency scaling
• Burst of 2 Read and Write
• 1.8 V +150/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
18Mb Burst of 2
DDR SigmaSIO-II SRAM
200 MHz–167 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
Bottom View
165-Bump, 13 mm x 15 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
JEDEC Std. MO-216, Variation CAB-1
routed internally to fire the output registers instead. Each Burst
of 2 SigmaSIO-II SRAM also supplies Echo Clock outputs,
CQ and CQ, which are synchronized with read data output.
When used in a source synchronous clocking scheme, the Echo
Clock outputs can be used to fire input registers at the data’s
destination.
Because Separate I/O Burst of 2 RAMs always transfer data in
two packets, A0 is internally set to 0 for the first read or write
transfer, and automatically incremented by 1 for the next
transfer. Because the LSB is tied off internally, the address
field of a Burst of 2 RAM is always one address pin less than
the advertised index depth (e.g., the 1M x 18 has a 512K
addressable index).
SigmaRAM™ Family Overview
GS8182S18 are built in compliance with the SigmaSIO-II
SRAM pinout standard for Separate I/O synchronous SRAMs.
They are 18,874,368-bit (18Mb) SRAMs. These are the first in
a family of wide, very low voltage HSTL I/O SRAMs designed
to operate at the speeds needed to implement economical high
performance networking systems.
Clocking and Addressing Schemes
A Burst of 2 SigmaSIO-II SRAM is a synchronous device. It
employs dual input register clock inputs, K and K. The device
also allows the user to manipulate the output register clock
input quasi independently with dual output register clock
inputs, C and C. If the C clocks are tied high, the K clocks are
Parameter Synopsis
-200
tKHKH
tKHQV
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
Rev: 1.09 7/2006
1/30
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-200/167
1M x 18 SigmaQuad SRAM—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
D
OFF
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/SA
(144Mb)
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
NC/SA
(36Mb)
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
NC
BW0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
V
SS
/SA
(72Mb)
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Notes:
1. Expansion addresses: A3 for 36Mb, A10 for 72Mb, A2 for 144Mb
2. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
Rev: 1.09 7/2006
2/30
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-200/167
Pin Description Table
Symbol
SA
NC
R/W
BW0–BW1
K
C
TMS
TDI
TCK
TDO
V
REF
ZQ
K
C
D
OFF
LD
CQ
CQ
D
Q
V
DD
V
DDQ
V
SS
Description
Synchronous Address Inputs
No Connect
Synchronous Read/Write
Synchronous Byte Writes
Input Clock
Output Clock
Test Mode Select
Test Data Input
Test Clock Input
Test Data Output
HSTL Input Reference Voltage
Output Impedance Matching Input
Input Clock
Output Clock
DLL Disable
Synchronous Load Pin
Output Echo Clock
Output Echo Clock
Synchronous Data Inputs
Synchronous Data Outputs
Power Supply
Isolated Output Buffer Supply
Power Supply: Ground
Type
Input
—
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
Input
Output
—
—
Output
Output
Input
Output
Supply
Supply
Supply
Comments
—
—
Active Low
Active High
Active High
—
—
—
—
—
—
Active Low
Active Low
Active Low
Active Low
Active Low
Active High
1.8 V Nominal
1.8 or 1.5 V Nominal
—
Notes:
1. C, C, K, or K cannot be set to V
REF
voltage.
2. When ZQ pin is directly connected to V
DD
, output impedance is set to minimum value and it cannot be connected to ground or left uncon-
nected.
3. NC = Not Connected to die or any other pin
Background
Separate I/O SRAMs, like SigmaQuad SRAMs, are attractive in applications where alternating reads and writes are needed. On the
other hand, Common I/O SRAMs like the SigmaCIO family are popular in applications where bursts of read or write traffic are
needed. The SigmaSIO SRAM is a hybrid of these two devices. Like the SigmaQuad family devices, the SigmaSIO features a
separate I/O data path, offering the user independent Data In and Data Out pins. However, the SigmaSIO devices offer a control
protocol like that offered on the SigmaCIO devices. Therefore, while SigmaQuad SRAMs allow a user to operate both data ports at
the same time, they force alternating loads of read and write addresses. SigmaSIO SRAMs allow continuous loads of read or write
addresses like SigmaCIO SRAMs, but in a separate I/O configuration.
Rev: 1.09 7/2006
3/30
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-200/167
Like a SigmaQuad SRAM, a SigmaSIO-II SRAM can execute an alternating sequence of reads and writes. However, doing so
results in the Data In port and the Data Out port stalling with nothing to do on alternate transfers. A SigmaQuad device would keep
both ports running at capacity full time. On the other hand, the SigmaSIO device can accept a continuous stream of read commands
and read data or a continuous stream of write commands and write data. The SigmaQuad device, by contrast, restricts the user from
loading a continuous stream of read or write addresses. The advantage of the SigmaSIO device is that it allows twice the random
address bandwidth for either reads or writes than could be acheived with a SigmaQuad version of the device. SigmaCIO SRAMs
offer this same advantage, but do not have the separate Data In and Data Out pins offered on the SigmaSIO SRAMs. Therefore,
SigmaSIO devices are useful in psuedo dual port SRAM applications where communication of burst traffic between two
electrically independent busses is desired.
Each of the three SigmaQuad Family SRAMs—SigmaQuad, SigmaCIO, and SigmaSIO—supports similar address rates because
random address rate is determined by the internal performance of the RAM. In addition, all three SigmaQuad Family SRAMs are
based on the same internal circuits. Differences between the truth tables of the different devices proceed from differences in how
the RAM’s interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and
disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to
the application at hand.
Burst of 2 SigmaSIO-II SRAM DDR Read
The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A high on
the R/W pin begins a read cycle. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C
are tied high), and after the following rising edge of K with a rising edge of C (or by K if C and C are tied high).
SigmaSIO-II Double Data Rate SRAM Read First
Read A
Write B
Read C
Write D
NOP
Read E
Read F
NOP
K
K
Address
LD
R/W
BWx
D
C
C
Q
CQ
CQ
A
A+1
C
C+1
E
E+1
F
B
B
B+1
B+1
D
D
D+1
D+1
A
B
C
D
E
F
Rev: 1.09 7/2006
4/30
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-200/167
Burst of 2 SigmaSIO-II SRAM DDR Write
The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A low on the
R/W pin, begins a write cycle. Data is clocked in by the next rising edge of K and then the rising edge of K.
SigmaSIO-II Double Data Rate SRAM Write First
Write A
Read B
NOP
Read C
Write D
NOP
Read E
Read F
NOP
K
K
Address
LD
R/W
BWx
D
C
C
Q
CQ
CQ
B
B+1
C
C+1
E
E+1
F
A
A
A+1
A+1
D
D
D+1
D+1
A
B
C
D
E
F
Rev: 1.09 7/2006
5/30
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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