19-1557; Rev 0; 10/99
+2.7V to +5.5V, Low-Power, Quad, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
General Description
The MAX5100 parallel-input, voltage-output, quad 8-bit
digital-to-analog converter (DAC) operates from a sin-
gle +2.7V to +5.5V supply and comes in a space-sav-
ing 20-pin TSSOP package. Internal precision buffers
swing Rail-to-Rail
®
, and the reference input range
includes both ground and the positive rail. All four
DACs share a common reference input.
The MAX5100 provides double-buffered logic inputs:
four 8-bit buffer registers followed by four 8-bit DAC
registers. This keeps the DAC outputs from changing
during the write operation. An asynchronous control
pin,
LDAC,
allows for simultaneous updating of the
DAC registers.
The MAX5100 features a shutdown mode that reduces
current to 1nA, as well as a power-on reset mode that
resets all registers to code 00 hex on power-up.
o
Ultra-Low Supply Current
0.4mA while Operating
1nA in Shutdown Mode
o
Ultra-Small 20-Pin TSSOP Package
o
Ground to V
DD
Reference Input Range
o
Output Buffer Amplifiers Swing Rail-to-Rail
o
Double-Buffered Registers for Synchronous
Updating
o
Power-On Reset Sets All Registers to Zero
Features
o
+2.7V to +5.5V Single-Supply Operation
MAX5100
Ordering Information
PART
MAX5100AEUP
MAX5100BEUP
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
20 TSSOP
20 TSSOP
INL
(LSB)
±1
±2
Applications
Digital Gain and Offset Adjustments
Programmable Attenuators
Portable Instruments
Power-Amp Bias Control
TOP VIEW
OUTB 1
OUTA 2
V
DD
3
REF 4
SHDN 5
WR 6
D7 7
D6 8
D5 9
D4 10
20 OUTC
19 OUTD
18 GND
17 A0
Pin Configuration
MAX5100
16 A1
15 LDAC
14 D0
13 D1
12 D2
11 D3
TSSOP
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
________________________________________________________________
Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
+2.7V to +5.5V, Low-Power, Quad, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
MAX5100
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND ..............................................................-0.3V to +6V
D_, A_,
WR,
SHDN,
LDAC
to GND...........................-0.3V to +6V
REF to GND ................................................-0.3V to (V
DD
+ 0.3V)
OUT_ to GND ...........................................................-0.3V to V
DD
Maximum Current into Any Pin .........................................±50mA
Continuous Power Dissipation (T
A
= +70°C)
20-Pin TSSOP (derate 7.0mW/°C above +70°C) .......559mW
Operating Temperature Range
MAX5100_EUP ..............................................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= V
REF
= +2.7V to +5.5V, R
L
= 10kΩ, C
L
= 100pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V
DD
= V
REF
= +3V and T
A
= +25°C.)
PARAMETER
STATIC ACCURACY
Resolution
Integral Nonlinearity (Note 1)
Differential Nonlinearity (Note 1)
Zero-Code Error
Zero-Code-Error Supply
Rejection
Zero-Code Temperature
Coefficient
Gain Error (Note 2)
Gain-Error Temperature
Coefficient
INL
DNL
ZCE
MAX5100A
MAX5100B
Guaranteed monotonic
Code = 00 hex
Code = 00 hex, V
DD
= 2.7V to 5.5V
Code = 00 hex
Code = F0 hex
Code = F0 hex
V
DD
= 2.7V to 3.6V,
V
REF
= 2.5V
V
DD
= 4.5V to 5.5V,
V
REF
= 4.096V
REFERENCE INPUT
Input Voltage Range
Input Resistance
Input Capacitance
DAC OUTPUTS
Output Voltage Range
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
Input Capacitance
2
V
IH
V
IL
I
IN
C
IN
V
IN
= V
DD
or GND
10
R
L
=
∞
V
DD
= 2.7V to 3.6V
V
DD
= 3.6V to 5.5V
0
2
3
0.8
±1.0
0
320
460
15
V
REF
V
DD
600
V
kΩ
pF
V
±0.001
1
LSB
1
±10
±1
8
±1
±2
±1
±20
10
Bits
LSB
LSB
mV
mV
µV/°C
%
LSB/°C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Power-Supply Rejection
Code = FF hex
V
V
µA
pF
_______________________________________________________________________________________
+2.7V to +5.5V, Low-Power, Quad, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= V
REF
= +2.7V to +5.5V, R
L
= 10kΩ, C
L
= 100pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V
DD
= V
REF
= +3V and T
A
= +25°C.)
PARAMETER
DYNAMIC PERFORMANCE
Output Voltage Slew Rate
Output Settling Time (Note 3)
Channel-to-Channel Isolation
(Note 4)
Digital Feedthrough (Note 5)
Digital-to-Analog Glitch Impulse
From code 00 to code F0 hex
To 1/2LSB, from code 10 to code F0 hex
Code 00 to code FF hex
Code 00 to code FF hex
Code 80 hex to code 7F hex
REF = 2.5Vp-p at
1kHz
REF = 2.5Vp-p at
10kHz
0.6
6
500
0.5
90
70
dB
60
650
60
t
SDR
t
SDN
V
DD
I
DD
To ±1/2LSB of final value of V
OUT
I
DD
< 5µA
2.7
370
0.001
t
AS
t
AH
t
DS
t
DH
t
WR
t
LD
5
0
25
0
20
20
13
20
5.5
700
1
kHz
µV
RMS
µs
µs
V
µA
µA
ns
ns
ns
ns
ns
ns
V/µs
µs
nVs
nVs
nVs
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX5100
Signal-to-Noise plus Distortion
Ratio
SINAD
V
REF(DC)
= 1.5V,
V
DD
= 3V,
code = FF hex
Multiplying Bandwidth
Wideband Amplifier Noise
Shutdown Recovery Time
Time to Shutdown
POWER SUPPLIES
Power-Supply Voltage
Supply Current (Note 6)
Shutdown Current
DIGITAL TIMING
(Figure 1) (Note 7)
Address to
WR
Setup
Address to
WR
Hold
Data to
WR
Setup
Data to
WR
Hold
WR
Pulse Width
LDAC
Pulse Width (Note 8)
REF = 0.5Vp-p, V
REF(DC)
= 1.5V,
V
DD
= 3V, -3dB bandwidth
Note 1:
Reduced digital code range (code 00 hex to code F0 hex) due to swing limitations when the output amplifier is loaded.
Note 2:
Gain error is: [100 (V
F0,meas
- ZCE - V
F0,ideal
) / V
REF
]. Where V
F0,meas
is the DAC output voltage with input code F0 hex,
and V
F0,ideal
is the ideal DAC output voltage with input code F0 hex (i.e., V
REF
·
240 / 256).
Note 3:
Output settling time is measured from the 50% point of the falling edge of
WR
to ±1/2LSB of V
OUT
’s final value.
Note 4:
Channel-to-channel isolation is defined as the glitch energy at a DAC output in response to a full-scale step change on any
other DAC output. The measured channel has a fixed code of 80 hex.
Note 5:
Digital feedthrough is defined as the glitch energy at any DAC output in response to a full-scale step change on all eight
data inputs with
WR
at V
DD
.
Note 6:
R
L
=
∞,
digital inputs at GND or V
DD
.
Note 7:
Timing measurement reference level is (V
IH
+ V
IL
) / 2.
Note 8:
If
LDAC
is activated prior to
WR’s
rising edge, it must stay low for t
LD
(or longer) after
WR
goes high.
_______________________________________________________________________________________
3
+2.7V to +5.5V, Low-Power, Quad, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
MAX5100
ADDRESS
t
AS
WR
ADDRESS VALID
t
WR
t
AH-
t
LD
LDAC (NOTE 8)
t
DS-
DATA
DATA VALID
t
DH-
Figure 1. Timing Diagram
Typical Operating Characteristics
(V
DD
= V
REF
= +3V, R
L
= 10kΩ, C
L
= 100pF, code = FF hex, T
A
= +25°C, unless otherwise noted.)
DAC ZERO-CODE OUTPUT VOLTAGE
vs. SINK CURRENT
MAX5100 toc01
DAC FULL-SCALE OUTPUT VOLTAGE
vs. SOURCE CURRENT
MAX5100 toc02
SUPPLY CURRENT vs. TEMPERATURE
320
SUPPLY CURRENT (µA)
300
280
260
240
220
V
DD
= 3V; CODE = F0 HEX
V
DD
= 5V; CODE = 00 HEX
1 DAC AT CODE 00 OR F0,
3 DACS AT 00 (R
L
=
∞)
V
DD
= 5V; CODE = F0 HEX
MAX5100 toc03
MAX5100 toc06
1.2
1.0
0.8
V
OUT
(V)
0.6
0.4
0.2
0
0
2
4
6
8
V
DD
= V
REF
= 5V
6
5
4
V
OUT
(V)
340
V
DD
= V
REF
= 3V
V
DD
= V
REF
= 5V
V
DD
= V
REF
= 3V
3
2
1
0
V
DD
= 3V; CODE = 00 HEX
200
180
0
2
4
6
8
10
-40
-20
0
20
40
60
80
100
SOURCE CURRENT (mA)
TEMPERATURE (°C)
10
SINK CURRENT (mA)
SUPPLY CURRENT vs. REFERENCE VOLTAGE
(V
DD
= 3V)
MAX5100 toc04
SUPPLY CURRENT vs. REFERENCE VOLTAGE
(V
DD
= 5V)
1 DAC AT CODE 00 OR F0, 3 DACS AT 00 (R
L
=
∞)
CODE = F0
MAX5100 toc05
TOTAL HARMONIC DISTORTION PLUS NOISE
AT DAC OUTPUT vs. REFERENCE AMPLITUDE
0
-10
-20
V
DD
= +3V
DAC CODE = FF HEX
V
REF
= SINE WAVE CENTERED AT 1.5V
80kHz FILTER
300
280
1 DAC AT CODE 00 OR F0, 3 DACS AT 00 (R
L
=
∞)
CODE = F0
320
300
SUPPLY CURRENT (µA)
280
260
240
220
SUPPLY CURRENT (µA)
260
240
220
200
180
160
140
0
0.5
1.0
1.5
2.0
2.5
3.0
REFERENCE VOLTAGE (V)
CODE = 00
THD + NOISE (dB)
-30
-40
20kHz REF SIGNAL
-50
-60
-70
10kHz REF SIGNAL
CODE = 00
200
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
REFERENCE VOLTAGE (V)
1kHz REF SIGNAL
-80
0
0.5
1.0
1.5
2.0
2.5
REFERENCE AMPLITUDE (V
p-p
)
4
_______________________________________________________________________________________
+2.7V to +5.5V, Low-Power, Quad, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
Typical Operating Characteristics (continued)
(V
DD
= V
REF
= +3V, R
L
= 10kΩ, C
L
= 100pF, code = FF hex, T
A
= +25°C, unless otherwise noted.)
MAX5100
TOTAL HARMONIC DISTORTION PLUS NOISE
AT DAC OUTPUT vs. REFERENCE FREQUENCY
-10
-20
THD + NOISE (dB)
-30
-40
-50
-60
-70
-80
1
10
FREQUENCY (kHz)
100
REF = 2V
p-p
REF = 0.5V
p-p
V
DD
= +3V
DAC CODE = FF HEX
V
REF
= SINE WAVE CENTERED AT 1.5V
1kHz FREQUENCY
500kHz FILTER
MAX5100 toc07
REFERENCE INPUT
FREQUENCY RESPONSE
MAX5100 toc08
WORST-CASE 1LSB DIGITAL STEP CHANGE
(NEGATIVE)
CH1 = LDAC, 2V/div
CH2 = V
OUTA
, 50mV/div,
AC-COUPLED
DAC CODE FROM
80 TO 7F HEX
1
MAX55100 toc09
MAX5100 toc15
MAX55100 toc12
0
10
0
-10
OUTPUT AMPLITUDE (dB)
-20
-30
-40
-50
-60
-70
-80
-90
CODE = FF HEX, REF IS 1V
p-p
SIGNAL
V
REF
= 1.5V
0.01
0.1
1
REF = 1V
p-p
2
10
1µs/div
FREQUENCY (MHz)
WORST-CASE 1LSB DIGITAL STEP CHANGE
(POSITIVE)
MAX55100 toc10
DIGITAL FEEDTHROUGH GLITCH IMPULSE
(0 TO 1 DIGITAL TRANSITION)
CH1 = D7, 2V/div
CH2 = V
OUTA
, 2mV/div,
AC-COUPLED
0 TO 1 DIGITAL TRANSITION ON
ALL DATA BITS (WITH WR HIGH,
LDAC LOW)
MAX55100 toc11
DIGITAL FEEDTHROUGH GLITCH IMPULSE
(1 TO 0 DIGITAL TRANSITION)
CH1 = D7, 2V/div
CH2 = V
OUTA
, 2mV/div,
AC-COUPLED
1 TO 0 DIGITAL TRANSITION ON
ALL DATA BITS (WITH WR HIGH,
LDAC LOW)
CH1 = LDAC, 2V/div
CH2 = V
OUTA
, 50mV/div,
AC-COUPLED
DAC CODE FROM
7F TO 80 HEX
1
2
1
2
1
2
1µs/div
20ns/div
20ns/div
POSITIVE SETTLING TIME
MAX55100 toc13
NEGATIVE SETTLING TIME
MAX55100 toc14
INTEGRAL AND DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
0.5
0.4
0.3
0.2
INL/DNL (LSB)
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
INL
DNL
R
L
=
∞
CH1 = WR, 2V/div
CH2 = V
OUTA
, 2V/div
DAC CODE FROM
10 TO F0 HEX
1
CH1 = WR, 2V/div
CH2 = V
OUTA
, 2V/div
DAC CODE FROM
10 TO F0 HEX
1
2
2
1µs/div
1µs/div
0
32
64
96
128 160 192 224 256
DIGITAL CODE
_______________________________________________________________________________________
5
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