GTL1655
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
Rev. 01 — 11 May 2004
Product data
1. Description
The GTL1655 is a 16-bit bus transceiver that incorporates HIGH-drive
LOW-output-impedance (100 mA/12
Ω)
with LVTTL-to-GTL/GTL+ and
GTL/GTL+-to-LVTTL logic level translation.
The device is configured as two 8-bit transceivers that share a common clock and a
master output enable pin, but also have individual latch timing and output enable
signals. D-type flip-flops and D-type latches enable three modes of data transfer;
Clocked, Latched, or Transparent. The GTL1655 provides the ideal interface between
cards operating at LVTTL levels and backplanes using GTL/GTL+ signal levels. The
combination of reduced output swing, reduced input threshold levels and configurable
edge control provides the higher speed operation of GTL/GTL+ backplanes.
The GTL1655 can be used at GTL (V
TT
= 1.2 V, V
REF
= 0.8 V) or GTL+ (V
TT
= 1.5 V,
V
REF
= 1.0 V) signalling levels. Port A and the control inputs are compliant with
LVTTL signal levels and are 5 V tolerant. Port B is designed to operate at GTL or
GTL+ signal levels, with V
REF
providing the reference voltage input.
The latch enable pins (nLEAB and nLEBA), the output enable pins (nOEAB, nOEBA)
and the clock pin (CP) are used to control the data flow through the two 8-bit
transceivers (n = 1 or 2). When nLEAB is set HIGH, the device will operate in the
transparent mode Port A to Port B. HIGH-to-LOW transitions of nLEAB will latch A
data independently of CP HIGH or LOW (latched mode). LOW-to-HIGH transitions of
CP will clock A data to the B port if nLEAB is LOW (clocked mode). Using the control
pins nLEBA, nOEBA and CP in the same way, data flow from Port B to Port A can be
controlled. The OE pin can be used to disable all of the I/O pins.
To optimize signal integrity, the GTL1655 features an adjustable edge rate control
(V
ERC
). By adjusting V
ERC
between GND and V
CC
, a designer can adjust the Port B
edge rate to suit an application’s load conditions.
The GTL1655 permits true live insertion capability by incorporating:
•
BIAS V
CC
, to pre-charge outputs and avoid disturbing active data during card
insertion.
•
I
off
to disable current flow through powered-off I/Os.
•
Power-up 3-state, which ensures outputs are high-impedance during power-up,
thus preventing bus contention issues. Once V
CC
is above 1.5 V, the power-up
3-state circuit relinquishes control of the outputs to the OE pin. To ensure the
outputs remain 3-state, the OE pin should be tied to V
CC
via a pull-up resistor.
Philips Semiconductors
GTL1655
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
2. Features
s
Combination of D-type latches and D-type flip-flops for transceiver operation in
clocked, latched or transparent mode
s
Logic level translation between LVTTL and GTL/GTL+ signals
s
HIGH-drive LOW-output-impedance (100 mA/12
Ω)
on Port B
s
Configurable rise and fall times on Port B
s
Supports live insertion (I
off
, Power-up 3-state, and BIAS V
CC
)
s
Bus Hold on Port A inputs
s
Over voltage tolerance on Port A
s
Minimized switching noise through use of distributed V
CC
and GND pins
s
Available in TSSOP64 package
s
Industrial temperature range (−40
°C
to +85
°C)
s
ESD protection
x
HBM EIA/JESD22-A114-A exceeds 2000 V
x
CDM EIA/JESD22-C101 exceeds 1000 V
s
Latch-up EIA/JEDS78 exceeds 200 mA
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns
Symbol
t
PLH
Parameter
propagation delay, nAn to nBn
Conditions
V
CC
= 3.3 V; V
ERC
= GND;
V
TT
= 1.5 V; V
REF
= 1 V
V
CC
= 3.3 V; V
ERC
= GND;
V
TT
= 1.5 V; V
REF
= 1 V
propagation delay, nBn to nAn
t
PHL
propagation delay, nAn to nBn
V
CC
= 3.3 V
V
CC
= 3.3 V; V
ERC
= GND;
V
TT
= 1.5 V; V
REF
= 1 V
V
CC
= 3.3 V; V
ERC
= GND;
V
TT
= 1.5 V; V
REF
= 1 V
propagation delay, nBn to nAn
C
i
C
I/O
input capacitance (control pins)
I/O capacitance, Port A
I/O capacitance, Port B
V
CC
= 3.3 V
V
i
= V
CC
or GND
V
i
= V
CC
or GND
V
i
= V
CC
or GND
Min
-
-
-
-
-
-
-
-
-
Typ
3.9
4.4
2.6
3.1
2.7
4.2
3
7
8
Max
-
-
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
pF
pF
pF
9397 750 12936
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 11 May 2004
2 of 23
Philips Semiconductors
GTL1655
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
4. Ordering information
Table 2:
Ordering information
Package
Name
Description
Version
SOT646-1
Type number
GTL1655DGG TSSOP64 plastic thin shrink small outline package; 64 leads;
body width 6.1 mm
Standard packing quantities and other packaging data are available at
www.philipslogic.com/packaging.
4.1 Ordering options
Table 3:
Part marking
Topside mark
GTL1655DGG
Temperature range
T
amb
=
−40 °C
to +85
°C
Type number
GTL1655DGG
9397 750 12936
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 11 May 2004
3 of 23
Philips Semiconductors
GTL1655
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
5. Pinning information
5.1 Pinning
1OEAB
1OEBA
V
CC
1A1
GND
1A2
1A3
GND
1A4
1
2
3
4
5
6
7
8
9
64 CP
63 1LEAB
62 1LEBA
61 V
ERC
60 GND
59 1B1
58 1B2
57 GND
56 1B3
55 1B4
54 1B5
53 GND
52 1B6
51 1B7
50 V
CC
GND 10
1A5 11
GND 12
1A6 13
1A7 14
V
CC
15
1A8 16
2A1 17
GND 18
2A2 19
2A3 20
GND 21
2A4 22
2A5 23
GND 24
2A6 25
GND 26
2A7 27
V
CC
28
2A8 29
GND 30
2OEAB 31
2OEBA 32
002aaa763
GTL1655DGG
49 1B8
48 2B1
47 GND
46 2B2
45 2B3
44 GND
43 2B4
42 2B5
41 V
REF
40 2B6
39 GND
38 2B7
37 2B8
36 BIAS_V
CC
35 2LEAB
34 2LEBA
33 OE
Fig 1. TSSOP64 pin configuration.
9397 750 12936
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 11 May 2004
4 of 23
Philips Semiconductors
GTL1655
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
5.2 Pin description
Table 4:
Symbol
1OEAB
1OEBA
V
CC
1A1 to 1A8
GND
Pin description
Pin
1
2
3, 15, 28, 50
Description
output enable 1A-to-1B (active-LOW)
output enable 1B-to-1A (active-LOW)
DC supply voltage
4, 6, 7, 9, 11, 13, data inputs/outputs port 1A
14, 16
5, 8, 10, 12, 18,
21, 24, 26, 30,
39, 44, 47, 53,
57, 60
17, 19, 20, 22,
23, 25, 27, 29
31
32
33
34
35
36
37, 38, 40, 42,
43, 45, 46, 48
41
49, 51, 52, 54,
55, 56, 58, 59
61
62
63
64
ground (0 V)
2A1 to 2A8
2OEAB
2OEBA
OE
2LEBA
2LEAB
BIAS_V
CC
2B8 to 2B1
V
REF
1B8 to 1B1
V
ERC
1LEBA
1LEAB
CP
data inputs/outputs port 2A
output enable 2A-to-2B (active-LOW)
output enable 2B-to-2A (active-LOW)
output enable, all I/O pins (active-LOW)
latch enable 2B-to-2A
latch enable 2A-to-2B
bias supply voltage
data inputs/outputs port 2B
reference voltage
data inputs/outputs port 1B
edge-rate control voltage Port B
latch enable 2B-to-2A
latch enable 1A-to-1B
clock input
9397 750 12936
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 11 May 2004
5 of 23
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