PSMN1R6-40YLC
22 August 2012
N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using
NextPower technology
Product data sheet
1. Product profile
1.1 General description
Logic level enhancement mode N-channel MOSFET in LFPAK package. This product
is designed and qualified for use in a wide range of industrial, communications and
domestic equipment.
1.2 Features and benefits
•
High reliability Power SO8 package, qualified to 150°C
•
Optimised for 4.5V Gate drive utilising NextPower Superjunction technology
•
Ultra low QG, QGD, & QOSS for high system efficiencies at low and high loads
•
Ultra low Rdson and low parasitic inductance
1.3 Applications
•
DC-to-DC converters
•
Load switching
•
Power OR-ing
•
Server power supplies
•
Sync rectifier
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
T
j
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
junction temperature
Conditions
25 °C ≤ T
j
≤ 150 °C
T
mb
= 25 °C; V
GS
= 10 V;
Fig. 1
T
mb
= 25 °C;
Fig. 2
[1]
Min
-
-
-
-55
Typ
-
-
-
-
Max
40
100
288
150
Unit
V
A
W
°C
Static characteristics
drain-source on-state
resistance
V
GS
= 4.5 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 12
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 12
Dynamic characteristics
Q
GD
gate-drain charge
V
GS
= 4.5 V; I
D
= 25 A; V
DS
= 20 V;
Fig. 14
-
15.3
-
nC
-
1.25
1.55
mΩ
-
1.45
1.8
mΩ
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NXP Semiconductors
PSMN1R6-40YLC
N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using
NextPower technology
Symbol
Q
G(tot)
Parameter
total gate charge
Conditions
V
GS
= 4.5 V; I
D
= 25 A; V
DS
= 20 V;
Fig. 14
Min
-
Typ
59
Max
-
Unit
nC
[1]
Continuous current is limited by package.
2. Pinning information
Table 2.
Pin
1
2
3
4
mb
Pinning information
Symbol Description
S
S
S
G
D
source
source
source
gate
mounting base; connected to
drain
G
mbb076
Simplified outline
Graphic symbol
D
S
1
2
3
4
LFPAK; Power-
SO8 (SOT1023)
3. Ordering information
Table 3.
Ordering information
Package
Name
PSMN1R6-40YLC
LFPAK;
Power-SO8
Description
Version
Plastic single-ended surface-mounted package (LFPAK); 4 leads SOT1023
Type number
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
DGR
V
GS
I
D
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
V
GS
= 10 V; T
mb
= 25 °C;
Fig. 1
V
GS
= 10 V; T
mb
= 100 °C;
Fig. 1
I
DM
P
tot
T
stg
PSMN1R6-40YLC
Conditions
25 °C ≤ T
j
≤ 150 °C
25 °C ≤ T
j
≤ 150 °C; R
GS
= 20 kΩ
Min
-
-
-20
[1]
[1]
Max
40
40
20
100
100
1304
288
150
Unit
V
V
V
A
A
A
W
°C
-
-
-
-
-55
peak drain current
total power dissipation
storage temperature
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C;
Fig. 4
T
mb
= 25 °C;
Fig. 2
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© NXP B.V. 2012. All rights reserved
Product data sheet
22 August 2012
2 / 14
NXP Semiconductors
PSMN1R6-40YLC
N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using
NextPower technology
Symbol
T
j
T
sld(M)
V
ESD
I
S
I
SM
E
DS(AL)S
Parameter
junction temperature
peak soldering temperature
electrostatic discharge voltage
Conditions
Min
-55
-
Max
150
260
-
Unit
°C
°C
kV
MM (JEDEC JESD22-A115)
1
Source-drain diode
source current
peak source current
T
mb
= 25 °C
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 100 A;
V
sup
≤ 40 V; R
GS
= 50 Ω; unclamped;
Fig. 3
[1]
400
I
D
(A)
300
[1]
-
-
100
1304
A
A
Avalanche ruggedness
non-repetitive drain-source
avalanche energy
-
391
mJ
Continuous current is limited by package.
003aag974
120
P
der
(%)
80
003aab937
200
40
100
(1)
0
0
50
100
150 T
mb
(°C)
200
0
0
50
100
150
T
mb
(°C)
200
Fig. 1.
Continuous drain current as a function of
mounting base temperature
Fig. 2.
Normalized total power dissipation as a
function of solder point temperature
PSMN1R6-40YLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
22 August 2012
3 / 14
NXP Semiconductors
PSMN1R6-40YLC
N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using
NextPower technology
10
3
I
AL
(A)
10
2
(1)
003aag975
10
(2)
1
10
-3
10
-2
10
-1
1
t
AL
(ms)
10
Fig. 3.
Single pulse avalanche rating; avalanche current as a function of avalanche time
10
4
I
D
(A)
10
3
Limit R
DSon
= V
DS
/ I
D
003aag976
t
p
=10 µ s
10
2
100 µ s
10
DC
1 ms
10 ms
100 ms
1
10
-1
10
-1
1
10
V
DS
(V)
10
2
Fig. 4.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance
from junction to
mounting base
Conditions
Fig. 5
Min
-
Typ
0.35
Max
0.43
Unit
K/W
PSMN1R6-40YLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
22 August 2012
4 / 14
NXP Semiconductors
PSMN1R6-40YLC
N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using
NextPower technology
1
Z
th(j-mb)
(K/W)
δ = 0.5
10
-1
003aag977
0.2
0.1
0.05
P
δ=
t
p
T
10
-2
0.02
single shot
t
p
t
T
10
-3
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
t
p
(s)
1
Fig. 5.
Transient thermal impedance from junction to mounting base as a function of pulse duration
6. Characteristics
Table 6.
Symbol
V
(BR)DSS
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C;
Fig. 10; Fig. 11
I
D
= 10 mA; V
DS
= V
GS
; T
j
= 150 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C
I
DSS
drain leakage current
V
DS
= 40 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 40 V; V
GS
= 0 V; T
j
= 150 °C
I
GSS
gate leakage current
V
GS
= 16 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -16 V; V
DS
= 0 V; T
j
= 25 °C
R
DSon
drain-source on-state
resistance
V
GS
= 4.5 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 12
V
GS
= 4.5 V; I
D
= 25 A; T
j
= 150 °C;
Fig. 12; Fig. 13
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 12
V
GS
= 10 V; I
D
= 25 A; T
j
= 150 °C;
Fig. 12; Fig. 13
R
G
gate resistance
f = 1 MHz
-
1.17
2.34
Ω
-
-
2.7
mΩ
-
1.25
1.55
mΩ
-
-
3.2
mΩ
0.5
-
-
-
-
-
-
-
-
-
-
-
-
1.45
-
2.25
1
100
100
100
1.8
V
V
µA
µA
nA
nA
mΩ
Min
40
36
1.05
Typ
-
-
1.46
Max
-
-
1.95
Unit
V
V
V
Static characteristics
V
GS(th)
PSMN1R6-40YLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
22 August 2012
5 / 14