19-1194; Rev 4; 4/11
KIT
ATION
EVALU
BLE
AVAILA
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
General Description
____________________________Features
o
2.7V to 5.5V Single Supply
o
Low Power: 85µA at 50ksps
6µA at 1ksps
o
8-Channel Single-Ended or 4-Channel Differential
Inputs (MAX1110)
o
4-Channel Single-Ended or 2-Channel Differential
Inputs (MAX1111)
o
Internal Track/Hold; 50kHz Sampling Rate
o
Internal 2.048V Reference
o
SPI/QSPI/MICROWIRE-Compatible Serial Interface
o
Software-Configurable Unipolar or Bipolar Inputs
o
Total Unadjusted Error: ±1 LSB (max)
±0.3 LSB (typ)
Ordering Information appears at end of data sheet.
MAX1110/MAX1111
The MAX1110/MAX1111 low-power, 8-bit, 8-channel
analog-to-digital converters (ADCs) feature an internal
track/hold, voltage reference, clock, and serial inter-
face. They operate from a single 2.7V to 5.5V supply
and consume only 85µA while sampling at rates up to
50ksps. The MAX1110’s 8 analog inputs and the
MAX1111’s 4 analog inputs are software-configurable,
allowing unipolar/bipolar and single-ended/differential
operation.
Successive-approximation conversions are performed
using either the internal clock or an external serial-inter-
face clock. The full-scale analog input range is deter-
mined by the 2.048V internal reference, or by an
externally applied reference ranging from 1V to V
DD
.
The 4-wire serial interface is compatible with the SPI™,
QSPI™, and MICROWIRE™ serial-interface standards.
A serial-strobe output provides the end-of-conversion
signal for interrupt-driven processors.
The MAX1110/MAX1111 have a software-program-
mable, 2µA automatic power-down mode to minimize
power consumption. Using power-down, the supply
current is reduced to 6µA at 1ksps, and only 52µA at
10ksps. Power-down can also be controlled using the
SHDN
input pin. Accessing the serial interface automat-
ically powers up the device.
The MAX1110 is available in a 20-pin SSOP package.
The MAX1111 is available in a small 16-pin QSOP
package.
________________Functional Diagram
CS
SCLK
DIN
SHDN
INPUT
SHIFT
REGISTER
INT
CLOCK
CONTROL
LOGIC
OUTPUT
SHIFT
REGISTER
ANALOG
INPUT
MUX
T/H
CLOCK
IN
8-BIT
SAR ADC
OUT
REF
DOUT
SSTRB
________________________Applications
Portable Data Logging
Hand-Held Measurement Devices
Medical Instruments
System Diagnostics
Solar-Powered Remote Systems
4mA to 20mA-Powered Remote
Data-Acquisition Systems
Pin Configurations appear at end of data sheet.
CH0
CH1
CH2
CH3
CH4*
CH5*
CH6*
CH7*
COM
REFOUT
REFIN
V
DD
DGND
+2.048V
REFERENCE
MAX1110
MAX1111
AGND
*MAX1110 ONLY
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
MAX1110/MAX1111
ABSOLUTE MAXIMUM RATINGS
V
DD
to AGND ..............................................................-0.3V to 6V
AGND to DGND .......................................................-0.3V to 0.3V
CH0–CH7, COM, REFIN,
REFOUT to AGND ......................................-0.3V to (V
DD
+ 0.3V)
Digital Inputs to DGND ...............................................-0.3V to 6V
Digital Outputs to DGND ............................-0.3V to (V
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
QSOP (derate 8.30mW/°C above +70°C) .....................667mW
SSOP (derate 8.00mW/°C above +70°C) .....................640mW
Operating Temperature Ranges
MAX1110CAP/MAX1111CEE...............................0°C to +70°C
MAX1110EAP/MAX1111EGE............................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 2.7V to 5.5V; unipolar input mode; V
COM
= 0V; f
SCLK
= 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle
(50ksps); 1µF capacitor at REFOUT; T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
PARAMETER
DC ACCURACY
Resolution
Relative Accuracy (Note 1)
Differential Nonlinearity
Offset Error
Gain Error (Note 3)
Gain Temperature Coefficient
Total Unadjusted Error
Channel-to-Channel
Offset Matching
DYNAMIC SPECIFICATIONS (10.034kHz sine-wave input, 2.048V
P-P
, 50ksps, 500kHz external clock)
Signal-to-Noise
and Distortion Ratio
Total Harmonic Distortion
(up to the 5th harmonic)
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
Small-Signal Bandwidth
Full-Power Bandwidth
SINAD
THD
SFDR
V
CH_
= 2.048V
P-P
, 25kHz (Note 4)
-3dB rolloff
49
-70
68
-75
1.5
800
dB
dB
dB
dB
MHz
kHz
TUE
INL
DNL
V
DD
= 2.7V to 3.6V
V
DD
= 5.5V (Note 2)
No missing codes over temperature
V
DD
= 2.7V to 3.6V
V
DD
= 5.5V (Note 2)
Internal or external reference
External reference, 2.048V
±0.8
±0.3
±0.1
±1
±0.35
±0.5
±1
8
±0.15
±0.2
±1
±1
±0.5
Bits
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 5.5V; unipolar input mode; V
COM
= 0V; f
SCLK
= 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle
(50ksps); 1µF capacitor at REFOUT; T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
PARAMETER
CONVERSION RATE
Conversion Time (Note 5)
Track/Hold Acquisition Time
Aperture Delay
Aperture Jitter
Internal Clock Frequency
External Clock-Frequency Range
ANALOG INPUT
Input Voltage Range, Single-
Ended and Differential (Note 7)
Multiplexer Leakage Current
Input Capacitance
INTERNAL REFERENCE
REFOUT Voltage
REFOUT Short-Circuit Current
REFOUT Temperature Coefficient
Load Regulation (Note 8)
Capacitive Bypass at REFOUT
EXTERNAL REFERENCE AT REFIN
Input Voltage Range
Input Current
POWER REQUIREMENTS
Supply Voltage
V
DD
V
DD
= 2.7V to 3.6V
Full-scale input
C
LOAD
= 10pF
Supply Current (Note 2)
I
DD
V
DD
= 5.5V
Full-scale input
C
LOAD
= 10pF
Power-down
Power-Supply Rejection
(Note 10)
PSR
Operating mode
Reference disabled
Operating mode
Reference disabled
Software
SHDN
at DGND
2.7
85
45
120
80
2
3.2
±0.4
10
±4
mV
250
µA
5.5
250
V
(Note 9)
1
1
V
DD
+
0.05
20
V
µA
0 to 0.5mA output load
1
1.968
2.048
3.5
±50
2.5
2.128
V
mA
ppm/°C
mV
µF
Unipolar input, V
COM
= 0V
Bipolar input, V
COM
= V
REFIN
/2
On/off-leakage current, V
CH_
= 0V or V
DD
±0.01
18
0
V
REFIN
V
COM
±
V
REFIN
/2
±1
V
V
µA
pF
(Note 6)
Used for data transfer only
50
t
CONV
t
ACQ
Internal clock
External clock, 500kHz, 10 clocks/conversion
External clock, 2MHz
20
1
10
<50
400
500
2
25
55
µs
µs
ns
ps
kHz
kHz
MHz
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX1110/MAX1111
V
DD
= 2.7V to 3.6V; external reference,
2.048V; full-scale input
_______________________________________________________________________________________
3
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
MAX1110/MAX1111
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 5.5V; unipolar input mode; V
COM
= 0V; f
SCLK
= 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle
(50ksps); 1µF capacitor at REFOUT; T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
PARAMETER
DIGITAL INPUTS: DIN, SCLK,
CS
DIN, SCLK,
CS
Input High Voltage
DIN, SCLK,
CS
Input Low Voltage
DIN, SCLK,
CS
Input Hysteresis
DIN, SCLK,
CS
Input Leakage
DIN, SCLK,
CS
Input Capacitance
SHDN
INPUT
SHDN
Input High Voltage
SHDN
Input Mid-Voltage
SHDN
Voltage, High Impedance
SHDN
Input Low Voltage
SHDN
Input Current
SHDN
Maximum Allowed Leakage
for Mid-Input
DIGITAL OUTPUTS: DOUT, SSTRB
Output Low Voltage
Output High Voltage
Three-State Leakage Current
Three-State Output Capacitance
V
OL
V
OH
I
L
C
OUT
I
SINK
= 5mA
I
SINK
= 16mA
I
SOURCE
= 0.5mA
CS
= V
DD
CS
= V
DD
(Note 6)
V
DD
- 0.5
±0.01
±10
15
0.4
0.8
V
V
µA
pF
V
SH
V
SM
V
FLT
V
SL
V
SHDN
= 0V or V
DD
SHDN
= open
SHDN
= open
V
DD
- 0.4
1.1
V
DD
/2
0.4
±4
±100
V
DD
- 1.1
V
V
V
V
µA
nA
V
IH
V
IL
V
HYST
I
IN
C
IN
Digital inputs = 0V or V
DD
(Note 6)
0.2
±1
15
V
DD
≤
3.6V
V
DD
> 3.6V
2
3
0.8
V
V
V
µA
pF
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
4
_______________________________________________________________________________________
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
TIMING CHARACTERISTICS (Figures 8 and 9)
(V
DD
= 2.7V to 5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
Track/Hold Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
SCLK Fall to Output Data Valid
CS
Fall to Output Enable
CS
Rise to Output Disable
CS
to SCLK Rise Setup
CS
to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
CS
Fall to SSTRB Output Enable
(Note 6)
CS
Rise to SSTRB output
Disable (Note 6)
SSTRB Rise to SCLK Rise
(Note 6)
Wake-Up Time
SYMBOL
t
ACQ
t
DS
t
DH
t
DO
t
DV
t
TR
t
CSS
t
CSH
t
CH
t
CL
t
SSTRB
t
SDV
t
STR
t
SCK
t
WAKE
C
LOAD
= 100pF
Figure 1, external clock mode only,
C
LOAD
= 100pF
Figure 2, external clock mode only,
C
LOAD
= 100pF
Figure 11, internal clock mode only
External reference
Internal reference (Note 11)
0
20
12
Figure 1, C
LOAD
= 100pF
Figure 1, C
LOAD
= 100pF
Figure 2, C
LOAD
= 100pF
100
0
200
200
240
240
240
CONDITIONS
MIN
1
100
0
20
200
240
240
TYP
MAX
UNITS
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
MAX1110/MAX1111
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
See
Typical Operating Characteristics.
V
REFIN
= 2.048V, offset nulled.
On-channel grounded; sine wave applied to all off-channels.
Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Guaranteed by design. Not subject to production testing.
Common-mode range for the analog inputs is from AGND to V
DD
.
External load should not change during the conversion for specified accuracy.
External reference at 2.048V, full-scale input, 500kHz external clock.
Measured as
|
V
FS
(2.7V) - V
FS
(3.6V)
|.
1µF at REFOUT; internal reference settling to 0.5 LSB.
_______________________________________________________________________________________
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
