BUK9612-55B
N-channel TrenchMOS logic level FET
Rev. 02 — 4 June 2010
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
1.2 Features and benefits
Low conduction losses due to low
on-state resistance
Q101 compliant
Suitable for logic level gate drive
sources
Suitable for thermally demanding
environments due to 175 °C rating
1.3 Applications
12 V and 24 V loads
Automotive systems
General purpose power switching
Motors, lamps and solenoids
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
Quick reference data
Parameter
drain-source
voltage
drain current
total power
dissipation
drain-source
on-state
resistance
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
V
GS
= 5 V; T
mb
= 25 °C;
see
Figure 1;
see
Figure 3
T
mb
= 25 °C; see
Figure 2
[1]
Min
-
-
-
Typ
-
-
-
Max Unit
55
75
157
V
A
W
Static characteristics
R
DSon
V
GS
= 10 V; I
D
= 25 A;
T
j
= 25 °C
V
GS
= 5 V; I
D
= 25 A;
T
j
= 25 °C;
see
Figure 11;
see
Figure 12
-
-
9
10
mΩ
mΩ
10.2 12
Nexperia
BUK9612-55B
N-channel TrenchMOS logic level FET
Table 1.
Symbol
E
DS(AL)S
Quick reference data
…continued
Parameter
Conditions
Min
-
Typ
-
Max Unit
172
mJ
Avalanche ruggedness
non-repetitive
I
D
= 75 A; V
sup
≤
55 V;
drain-source
R
GS
= 50
Ω;
V
GS
= 5 V;
avalanche energy T
j(init)
= 25 °C; unclamped
gate-drain charge V
GS
= 5 V; I
D
= 25 A;
V
DS
= 44 V; T
j
= 25 °C;
see
Figure 13
Dynamic characteristics
Q
GD
-
12
-
nC
[1]
Continuous current is limited by package.
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
G
D
S
D
gate
drain
[1]
source
mounting base; connected to
drain
2
1
3
mb
D
Simplified outline
Graphic symbol
G
mbb076
S
SOT404 (D2PAK)
[1]
It is not possible to make a connection to pin 2.
3. Ordering information
Table 3.
Ordering information
Package
Name
BUK9612-55B
D2PAK
Description
Version
plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404
(one lead cropped)
Type number
BUK9612-55B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 02 — 4 June 2010
2 of 14
Nexperia
BUK9612-55B
N-channel TrenchMOS logic level FET
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
T
mb
= 25 °C; V
GS
= 5 V;
see
Figure 1;
see
Figure 3
T
mb
= 100 °C; V
GS
= 5 V; see
Figure 1
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
non-repetitive
drain-source
avalanche energy
T
mb
= 25 °C
t
p
≤
10 µs; pulsed; T
mb
= 25 °C
I
D
= 75 A; V
sup
≤
55 V; R
GS
= 50
Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped
[1]
[2]
[1]
[2]
[2]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
R
GS
= 20 kΩ
Min
-
-
-15
-
-
-
-
-
-55
-55
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
55
55
15
75
79
56
322
157
175
175
75
79
322
172
Unit
V
V
V
A
A
A
A
W
°C
°C
A
A
A
mJ
T
mb
= 25 °C; t
p
≤
10 µs; pulsed;
see
Figure 3
T
mb
= 25 °C; see
Figure 2
Source-drain diode
Avalanche ruggedness
[1]
[2]
Continuous current is limited by package.
Current is limited by power dissipation chip rating.
BUK9612-55B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 02 — 4 June 2010
3 of 14
Nexperia
BUK9612-55B
N-channel TrenchMOS logic level FET
80
I
D
(A)
60
03nn10
120
P
der
(%)
80
03na19
40
Capped at 75 A due to package
40
20
0
0
50
100
150
T
mb
(°C)
200
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Normalized continuous drain current as a
function of mounting base temperature
10
3
I
D
(A)
10
2
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
03nn08
Limit R
DSon
= V
DS
/I
D
t
p
= 10
µ
s
100
µ
s
Capped at 75 A due to package
1 ms
10 ms
100 ms
10
DC
1
1
10
V
DS
(V)
10
2
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
BUK9612-55B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 02 — 4 June 2010
4 of 14
Nexperia
BUK9612-55B
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance
from junction to
mounting base
thermal resistance
from junction to
ambient
Conditions
see
Figure 4
Min
-
Typ
-
Max
0.95
Unit
K/W
R
th(j-a)
minimum footprint ; mounted on a
printed-circuit board
-
50
-
K/W
1
03nn09
δ
= 0.5
Z
th(j-mb)
(K/W)
10
−1
0.2
0.1
0.05
0.02
10
−2
P
δ
=
t
p
T
single shot
t
p
t
T
10
−3
10
−6
10
−5
10
−4
10
−3
10
−2
10
−1
t
p
(s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK9612-55B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 02 — 4 June 2010
5 of 14
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
