Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1.0
IC, COLLECTOR CURRENT (AMP)
500
ms
0.5
1.0 ms
0.2
0.1
0.05
SECOND BREAKDOWN LIMIT
BONDING WIRE LIMIT
THERMAL LIMIT T
C
= 25°C
10
20
60
100
30 40
200
V
CE
, COLLECTOR-EMITTER VOLTAGE (VOLTS)
300
T
J
= 150°C
dc
ALL
ALL
0.02
0.01
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I
C
− V
CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation then the curves indicate.
The data of Figure 1 is based on T
J(pk)
= 150_C; T
C
is
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided T
J(pk)
≤
150_C. At high case temperatures, thermal limitations
will reduce the power that can be handled to values less then
the limitations imposed by second breakdown.
Figure 1. Active Region Safe Operating Area
300
200
T
J
= +150°C
hFE, CURRENT GAIN
100
70
50
30
20
+ 25°C
+100°C
VOLTAGE (VOLTS)
V
CE
= 2.0 V
V
CE
= 10 V
1.0
0.8
V
BE(sat)
@ I
C
/I
B
= 10
V
BE
@ V
CE
= 10 V
0.6
0.4
V
CE(sat)
@ I
C
/I
B
= 10
0.2
I
C
/I
B
= 5.0
T
J
= + 25°C
- 55°C
10
1.0
20
50 70 100
2.0 3.0 5.0 7.0 10
I
C
, COLLECTOR CURRENT (mA)
200 300 500
0
10
20
30
200 300
100
50
I
C
, COLLECTOR CURRENT (mA)
500
Figure 2. DC Current Gain
Figure 3. “On” Voltages
http://onsemi.com
2
MJE344G
PACKAGE DIMENSIONS
TO−225
CASE 77−09
ISSUE AC
4
1 2
3
FRONT VIEW
3 2
1
BACK VIEW
E
A1
Q
A
PIN 4
BACKSIDE TAB
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. NUMBER AND SHAPE OF LUGS OPTIONAL.
DIM
A
A1
b
b2
c
D
E
e
L
L1
P
Q
MILLIMETERS
MIN
MAX
2.40
3.00
1.00
1.50
0.60
0.90
0.51
0.88
0.39
0.63
10.60
11.10
7.40
7.80
2.04
2.54
14.50
16.63
1.27
2.54
2.90
3.30
3.80
4.20
D
P
1
2
3
L1
L
STYLE 1:
PIN 1. EMITTER
2., 4. COLLECTOR
3. BASE
2X
b2
2X
e
b
FRONT VIEW
c
SIDE VIEW
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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