v2.0
HiRel SX-A Family FPGAs
Features and Benefits
Leading Edge Performance
•
•
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215 MHz System Performance (Military Temperature)
5.3 ns Clock-to-Out (Pin-to-Pin) (Military Temperature)
240 MHz Internal Performance (Military Temperature)
•
•
•
•
•
•
•
•
•
•
•
Actel Secure Programming Technology with
FuseLock™ Prevents Reverse Engineering and Design
Theft
Cold-Sparing Capability
Individual Output Slew Rate Control
QML Certified Devices
100% Military Temperature Tested (–55°C to +125°C)
33 MHz PCI Compliant
CPLD and FPGA Integration
Single-Chip Solution
Configurable I/O Support for 3.3 V/5 V PCI, LVTTL,
and TTL
Configurable Weak Resistor Pull-Up or Pull-Down for
Tristated Outputs during Power-Up
Up to 100% Resource Utilization and 100% Pin
Locking
2.5 V, 3.3 V, and 5 V Mixed Voltage Operation with
5 V Input Tolerance and 5 V Drive Strength
Very Low Power Consumption
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
Boundary-Scan Testing in Compliance with IEEE
1149.1 (JTAG)
A54SX32A
32,000
48,000
2,880
1,800
1,080
1,980
228
3
0
Yes
Yes
5.3 ns
0 ns
Std, –1
84, 208, 256
A54SX72A
72,000
108,000
6,036
4,024
2,012
4,024
213
3
4
Yes
Yes
6.7 ns
0 ns
Std, –1
208, 256
Specifications
•
•
•
•
48,000 to 108,000 Available System Gates
Up to 228 User-Programmable I/O Pins
Up to 2,012 Dedicated Flip-Flops
0.25/0.22 µ CMOS Process Technology
Features
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•
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•
Hot-Swap Compliant I/Os
Power-Up/Down Friendly (no sequencing required
for supply voltages)
Class B Level Devices
Three Standard Hermetic Package Options
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Product Profile
Device
Capacity
Typical Gates
System Gates
Logic Modules
Combinatorial Cells
Register Cells
Dedicated Flip-Flops
Maximum Flip-Flops
Maximum User I/Os
Global Clocks
Quadrant Clocks
Boundary-Scan Testing
3.3 V / 5 V PCI
Clock-to-Out
Input Set-Up (External)
Speed Grades
Package (by Pin Count)
CQFP
N o ve m b e r 2 0 0 6
© 2006 Actel Corporation
i
See the Actel website for the latest version of the datasheet.
HiRel SX-A Family FPGAs
Ordering Information
A54SX32A – 1
CQ
208
M
Application (Ambient Temperature Range)
M = Military (–55 to +125°C)
B = MIL-STD-883 Class B
Package Lead Count
Package Type
CQ = Ceramic Quad Flat Pack
Speed Grade
Blank = Standard Speed
1 = Approximately 15% Faster than Standard
Part Number
A54SX32A = 48,000 System Gates
A54SX72A = 108,000 System Gates
Figure 1 •
HiRel SX-A Family Ordering Information
Ceramic Device Resources
User I/Os (including clock buffers)
Device
A54SX32A
A54SX72A
CQFP 84-Pin
62
–
CQFP 208-Pin
174
171
CQFP 256-Pin
228
213
Note:
Package Definitions: CQFP = Ceramic Quad Flat Pack
ii
v2.0
HiRel SX-A Family FPGAs
Actel MIL-STD-883 Product Flow
Step
1.
2.
3.
4.
Internal Visual
Temperature Cycling
Constant Acceleration
Seal
a. Fine
b. Gross
Visual Inspection
Pre-Burn-In Electrical Parameters
Burn-In Test
Interim (Post-Burn-In) Electrical Parameters
Percent Defective Allowable
Final Electrical Test
a. Static Tests
(1) 25°C (Subgroup 1, Table I)
(2) –55°C and +125°C
(Subgroups 2 and 3, Table I)
b. Functional Tests
(1) 25°C (Subgroup 7, Table I)
(2) –55°C and +125°C
(Subgroups 8A and 8B, Table I)
c. Switching Tests at 25°C
(Subgroup 9, Table I)
11.
External Visual
Screen
2010, Test Condition B
1010, Test Condition C
2001, Test Condition D, Y
1
, Orientation Only
1014
100%
100%
2009
In accordance with applicable Actel device specification
1015, Condition D, 160 hours @ 125°C or 80 hours @ 150°C
In accordance with applicable Actel device specification
5%
In accordance with applicable Actel device specification,
which includes a, b, and c:
100%
5005
5005
100%
5005
5005
5005
2009
100%
100%
100%
100%
100%
100%
All Lots
883 Method
883 – Class B
Requirement
100%
100%
100%
5.
6.
7.
8.
9.
10.
v2.0
iii
HiRel SX-A Family FPGAs
Table of Contents
General Description
QML Certification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
HiRel SX-A Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Detailed Specifications
2.5 V/3.3 V/5 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
5 V PCI Compliance for the HiRel SX-A Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
3.3 V PCI Compliance for the HiRel SX-A Family . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Junction Temperature (T
J
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
HiRel SX-A Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31
Package Pin Assignments
84-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
256-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
International Traffic in Arms Regulations (ITAR) and Export Administration
Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
iv
v 2 .0
HiRel SX-A Family FPGAs
General Description
The HiRel versions of Actel SX-A family FPGAs offer
advantages for commercial applications and all types of
military and high reliability equipment.
The HiRel versions are fully pin compatible, allowing
designs to migrate across different applications that do
not have radiation requirements. Additionally, the HiRel
devices can be used as a lower cost prototyping tool for
RadTolerant (RT) designs. This datasheet discusses HiRel
SX-A products. Refer to the
Actel website
for more
information concerning RadTolerant products.
The programmable architecture of these devices offers
high performance, design flexibility, and fast and
inexpensive prototyping, all without the expense of test
vectors, NRE charges, long lead times, and schedule and
cost penalties for design modifications that are often
required by ASIC devices.
Many suppliers of microelectronics components have
implemented QML as their primary worldwide business
system. Appropriate use of this system not only helps in
the implementation of advanced technologies, but also
allows for quality, reliable, and cost-effective logistics
support throughout the life cycles of QML products.
HiRel SX-A Family Architecture
The HiRel SX-A family architecture was designed to
satisfy next-generation performance and integration
requirements for production volume designs in a broad
range of applications.
Programmable Interconnect Element
The HiRel SX-A family incorporates either three (in HiRel
A54SX32A) or four (in HiRel A54SX72A) layers of metal
interconnect and provides efficient use of silicon by
locating the routing interconnect resources between the
top two metal layers (Figure
1-1).
This completely
eliminates the channels of routing and interconnect
resources between logic modules (as implemented on
SRAM FPGAs and previous generations of antifuse
FPGAs) and enables the entire floor of the device to be
spanned with an uninterrupted grid of logic modules.
QML Certification
Actel has achieved full QML certification, demonstrating
that quality management, procedures, processes, and
controls are in place and comply with MIL-PRF-38535, the
performance specification used by the Department of
Defense for monolithic integrated circuits. QML certification
is an example of the Actel commitment to supplying the
highest quality products for all types of high reliability,
military, and space applications.
Routing Tracks
Amorphous Silicon/
Dielectric Antifuse
Tungsten Plug Via
Metal 4
Metal 3
Tungsten Plug Via
Metal 2
Metal 1
Tungsten Plug Contact
Silicon Substrate
Note:
HiRel A54SX72A has four layers of metal with the antifuse between Metal 3 and Metal 4. HiRel A54SX32A has three layers of metal
with antifuse between Metal 2 and Metal 3.
Figure 1-1 •
HiRel SX-A Family Interconnect Elements
v2.0
1-1
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